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Parallel computations on reconfigurable meshes
R Miller, VK Prasanna-Kumar, DI Reisis, QF Stout
IEEE Transactions on Computers 42 (6), 678-692, 1993
3781993
Meshes with reconfigurable buses
R Miller, VKP Kumar, D Reisis, QF Stout
Proc. 15th MIT Conference on Advance Research in VLSI, 163-178, 1988
3091988
Image computations on meshes with multiple broadcast
VK Prasanna-Kumar, D Reisis
IEEE Transactions on Pattern Analysis and Machine Intelligence 11 (11), 1194 …, 1989
1011989
Image computations on reconfigurable VLSI arrays
R Miller, VK Prasanna-Kumar, DI Reisis, QF Stout
Proceedings CVPR'88: The Computer Society Conference on Computer Vision and …, 1988
821988
Conflict-free parallel memory accessing techniques for FFT architectures
D Reisis, N Vlassopoulos
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (11), 3438-3447, 2008
662008
NEPHELE: An end-to-end scalable and dynamically reconfigurable optical architecture for application-aware SDN cloud data centers
P Bakopoulos, K Christodoulopoulos, G Landi, M Aziz, E Zahavi, ...
IEEE Communications Magazine 56 (2), 178-188, 2018
592018
Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution
G Georgis, G Lentaris, D Reisis
Journal of real-time image processing 16 (4), 1207-1234, 2019
432019
A real-time motion estimation FPGA architecture
K Babionitakis, GA Doumenis, G Georgakarakos, G Lentaris, K Nakos, ...
Journal of Real-Time Image Processing 3, 3-20, 2008
372008
Reduced complexity superresolution for low-bitrate video compression
G Georgis, G Lentaris, D Reisis
IEEE Transactions on Circuits and Systems for Video Technology 26 (2), 332-345, 2015
332015
An efficient multiple precision floating-point multiplier
K Manolopoulos, D Reisis, VA Chouliaras
2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011
332011
An efficient multiple precision floating-point multiply-add fused unit
K Manolopoulos, D Reisis, VA Chouliaras
Microelectronics journal 49, 10-18, 2016
322016
High performance accelerator for cnn applications
A Kyriakos, V Kitsakis, A Louropoulos, EA Papatheofanous, I Patronas, ...
2019 29th international symposium on power and timing modeling, optimization …, 2019
262019
An efficient dual-mode floating-point multiply-add fused unit
K Manolopoulos, D Reisis, VA Chouliaras
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
242010
A real-time H. 264/AVC VLSI encoder architecture
K Babionitakis, G Doumenis, G Georgakarakos, G Lentaris, K Nakos, ...
Journal of Real-Time Image Processing 3, 43-59, 2008
242008
Parallel Image Processing On Enhanced Arrays.
DI Reisis, VK Prasanna
ICPP, 909-912, 1987
241987
FPGA & VPU co-processing in space applications: Development and testing with DSP/AI benchmarks
V Leon, C Bezaitis, G Lentaris, D Soudris, D Reisis, EA Papatheofanous, ...
2021 28th IEEE international conference on electronics, circuits, and …, 2021
212021
LDPC hardware acceleration in 5G open radio access network platforms
EA Papatheofanous, D Reisis, K Nikitopoulos
IEEE Access 9, 152960-152971, 2021
212021
Efficient parallel algorithms for intermediate level vision analysis on the reconfigurable mesh
R Miller, VKP Kumar, D Reisis, Q Stout
Parallel Architectures and Algorithms for Image Understanding, 185-207, 1991
211991
An efficient convex hull computation on the reconfigurable mesh
DI Reisis
Proceedings Sixth International Parallel Processing Symposium, 142-145, 1992
201992
A novel architecture for efficient protocol processing in high speed communication environments
G Konstantoulakis, V Nellas, C Georgopoulos, T Orphanoudakis, ...
1st European Conference on Universal Multiservice Networks. ECUMN'2000 (Cat …, 2000
192000
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