Luca Bertaccini
Luca Bertaccini
PhD Student, ETH Zurich
Verified email at
Cited by
Cited by
RedMulE: A compact FP16 matrix-multiplication accelerator for adaptive deep learning on RISC-V-based ultra-low-power SoCs
Y Tortorella, L Bertaccini, D Rossi, L Benini, F Conti
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
MiniFloat-NN and ExSdotp: An ISA extension and a modular open hardware unit for low-precision training on RISC-V cores
L Bertaccini, G Paulin, T Fischer, S Mach, L Benini
2022 IEEE 29th Symposium on Computer Arithmetic (ARITH), 1-8, 2022
To buffer, or not to buffer? a case study on FFT accelerators for ultra-low-power multicore clusters
L Bertaccini, L Benini, F Conti
2021 IEEE 32nd International Conference on Application-specific Systems …, 2021
Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores
L Bertaccini, M Perotti, S Mach, PD Schiavone, F Zaruba, L Benini
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
RVfplib: A fast and compact open-source floating-point emulation library for tiny RISC-V processors
M Perotti, G Tagliavini, S Mach, L Bertaccini, L Benini
International Conference on Embedded Computer Systems, 16-32, 2021
RedMule: A mixed-precision matrix–matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration
Y Tortorella, L Bertaccini, L Benini, D Rossi, F Conti
Future Generation Computer Systems 149, 122-135, 2023
Soft tiles: Capturing physical implementation flexibility for tightly-coupled parallel processing clusters
G Paulin, M Cavalcante, P Scheffler, L Bertaccini, Y Zhang, F Gürkaynak, ...
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 44-49, 2022
A 10-core soc with 20 fine-grain power domains for energy-proportional data-parallel processing over a wide voltage and temperature range
T Benz, L Bertaccini, F Zaruba, F Schuiki, FK Gürkaynak, L Benini
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
MiniFloats on RISC-V Cores: ISA Extensions with Mixed-Precision Short Dot Products
L Bertaccini, G Paulin, M Cavalcante, T Fischer, S Mach, L Benini
IEEE Transactions on Emerging Topics in Computing, 2024
ECHOES: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays
M Sinigaglia, L Bertaccini, L Valente, A Garofalo, S Benatti, L Benini, ...
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform
V Potocnik, L Colagrande, T Fischer, L Bertaccini, DJ Pagliari, A Burrello, ...
arXiv preprint arXiv:2405.19284, 2024
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