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Matteo Perotti
Matteo Perotti
Verified email at iis.ee.ethz.ch
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A “New Ara” for vector computing: an open source highly efficient RISC-V V 1.0 vector processor design
M Perotti, M Cavalcante, N Wistoff, R Andri, L Cavigelli, L Benini
2022 IEEE 33rd International Conference on Application-specific Systems …, 2022
252022
Spatz: A compact vector processing unit for high-performance and energy-efficient shared-L1 clusters
M Cavalcante, D Wüthrich, M Perotti, S Riedel, L Benini
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
122022
Darkside: A heterogeneous risc-v compute cluster for extreme-edge on-chip dnn inference and training
A Garofalo, Y Tortorella, M Perotti, L Valente, A Nadalini, L Benini, ...
IEEE Open Journal of the Solid-State Circuits Society 2, 231-243, 2022
122022
Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores
L Bertaccini, M Perotti, S Mach, PD Schiavone, F Zaruba, L Benini
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
62021
Quark: An integer RISC-V vector processor for sub-byte quantized DNN inference
MH AskariHemmat, T Dupuis, Y Fournier, N El Zarif, M Cavalcante, ...
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023
52023
HW/SW approaches for RISC-V code size reduction
M Perotti, P Davide, G Tagliavini, D Rossi, T Kurd, M Hill, L Yingying, ...
52020
RVfplib: A fast and compact open-source floating-point emulation library for tiny RISC-V processors
M Perotti, G Tagliavini, S Mach, L Bertaccini, L Benini
International Conference on Embedded Computer Systems, 16-32, 2021
42021
Darkside: 2.6 GFLOPS, 8.7 mW heterogeneous RISC-V cluster for extreme-edge on-chip DNN inference and training
A Garofalo, M Perotti, L Valente, Y Tortorella, A Nadalini, L Benini, ...
ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022
32022
Yun: An open-source, 64-bit RISC-V-Based vector processor with multi-precision integer and floating-point support in 65-nm CMOS
M Perotti, M Cavalcante, A Ottaviano, J Liu, L Benini
IEEE Transactions on Circuits and Systems II: Express Briefs, 2023
22023
AXI-pack: Near-memory bus packing for bandwidth-efficient irregular workloads
C Zhang, P Scheffler, T Benz, M Perotti, L Benini
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
22023
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications
M Rogenmoser, A Ottaviano, T Benz, R Balas, M Perotti, A Garofalo, ...
arXiv preprint arXiv:2406.06546, 2024
2024
Ara2: Exploring Single-and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor
M Perotti, M Cavalcante, R Andri, L Cavigelli, L Benini
IEEE Transactions on Computers, 2024
2024
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV
C Zhang, P Scheffler, T Benz, M Perotti, L Benini
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024
2024
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
M Perotti, Y Zhang, M Cavalcante, E Mustafa, L Benini
arXiv preprint arXiv:2401.04012, 2024
2024
Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication
J Schönleber, L Cavigelli, R Andri, M Perotti, L Benini
arXiv preprint arXiv:2311.10207, 2023
2023
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
M Cavalcante, M Perotti, S Riedel, L Benini
arXiv preprint arXiv:2309.10137, 2023
2023
Design of an OS compliant memory system for LEN5, a RISC-V Out of Order processor
M Perotti
Politecnico di Torino, 2019
2019
MX: Ultra-Low Overhead, Energy-Efficient Matrix Multiplication on RISC-V Vector ISA
M Perotti, Y Zhang, M Cavalcante, E Mustafa, L Benini
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