Doug Burger
Doug Burger
Technical Fellow, Microsoft Azure
Verified email at microsoft.com - Homepage
Title
Cited by
Cited by
Year
The SimpleScalar tool set, version 2.0
D Burger, TM Austin
ACM SIGARCH Computer Architecture News 25 (3), 13-25, 1997
43991997
Dark silicon and the end of multicore scaling
H Esmaeilzadeh, E Blem, RS Amant, K Sankaralingam, D Burger
2011 38th Annual international symposium on computer architecture (ISCA …, 2011
19392011
Modeling the effect of technology trends on the soft error rate of combinational logic
P Shivakumar, M Kistler, SW Keckler, D Burger, L Alvisi
Proceedings International Conference on Dependable Systems and Networks, 389-398, 2002
17982002
Architecting phase change memory as a scalable dram alternative
BC Lee, E Ipek, O Mutlu, D Burger
Proceedings of the 36th annual international symposium on Computer …, 2009
14922009
A reconfigurable fabric for accelerating large-scale datacenter services
A Putnam, AM Caulfield, ES Chung, D Chiou, K Constantinides, J Demme, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
10152014
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
C Kim, D Burger, SW Keckler
ACM SIGPLAN Notices 37 (10), 211-222, 2002
9522002
Clock rate versus IPC: The end of the road for conventional microarchitectures
V Agarwal, MS Hrishikesh, SW Keckler, D Burger
ACM SIGARCH Computer Architecture News 28 (2), 248-259, 2000
9352000
Better I/O through byte-addressable, persistent memory
J Nightingale, C Frost, EIB Lee, DBD Coetzee
22nd symposium on Operating systems principles (SOSP'09), 133-146, 2009
913*2009
ªEvaluating Future Microprocessors: The Simplescalar Toolset
D Burger, T Austin, S Bennett
º Technical Report CS-TR-96-1308, Computer Sciences Dept., Univ. of …, 1996
7991996
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, D Burger, ...
30th Annual International Symposium on Computer Architecture, 2003 …, 2003
6742003
Neural acceleration for general-purpose approximate programs
H Esmaeilzadeh, A Sampson, L Ceze, D Burger
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 449-460, 2012
6422012
Memory bandwidth limitations of future microprocessors
D Burger, JR Goodman, A Kägi
ACM SIGARCH Computer Architecture News 24 (2), 78-89, 1996
581*1996
Architecture support for disciplined approximate programming
H Esmaeilzadeh, A Sampson, L Ceze, D Burger
Proceedings of the seventeenth international conference on Architectural …, 2012
4762012
Scaling to the End of Silicon with EDGE Architectures
D Burger, SW Keckler, KS McKinley, M Dahlin, LK John, C Lin, CR Moore, ...
Computer 37 (7), 44-55, 2004
4582004
A NUCA substrate for flexible CMP cache sharing
J Huh, C Kim, H Shafi, L Zhang, D Burger, SW Keckler
IEEE transactions on parallel and distributed systems 18 (8), 1028-1040, 2007
4562007
Phase-change technology and the future of main memory
BC Lee, P Zhou, J Yang, Y Zhang, B Zhao, E Ipek, O Mutlu, D Burger
Micro, IEEE 30 (1), 143-143, 2010
4292010
A cloud-scale acceleration architecture
AM Caulfield, ES Chung, A Putnam, H Angepat, J Fowers, M Haselman, ...
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
4232016
Use ECP, not ECC, for hard failures in resistive memories
S Schechter, GH Loh, K Straus, D Burger
ACM SIGARCH Computer Architecture News 38 (3), 141-152, 2010
3772010
Computer science handbook
AB Tucker
CRC press, 2004
3492004
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
MS Hrishikesh, NP Jouppi, KI Farkas, D Burger, SW Keckler, ...
Proceedings 29th Annual International Symposium on Computer Architecture, 14-24, 2002
3352002
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