Ramesh Harjani

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Sachin SapatnekarUniversity of MinnesotaVerified email at umn.edu
Bodhisatwa SadhuResearch Scientist & IBM Master Inventor, IBM T. J. Watson Labs, Yorktown Heights, NY - 10598Verified email at us.ibm.com
Meghna MadhusudanUniversity of MinnesotaVerified email at umn.edu
Arvind SharmaR&D Engineer @ imecVerified email at imec.be
Jiang HuProfessor of Electrical and Computer Engineering, Texas A&M UniversityVerified email at tamu.edu
Byunghoo JungPurdue UniversityVerified email at purdue.edu
Rob A. RutenbarProfessor of Computer Science and Electrical and Computer Engineering, University of PittsburghVerified email at pitt.edu
Jitesh PoojaryUniversity of MinnesotaVerified email at umn.edu
Mohammad ElbadryBroadcomVerified email at broadcom.com
Satwik PatnaikRF Design Engineer, AmazonVerified email at amazon.com
Kishor KunalUniversity of Minnesota, Twin citiesVerified email at umn.edu
Mustafijur RahmanIndian Institute of Technology DelhiVerified email at ee.iitd.ac.in
Tonmoy DharUniversity of MinnesotaVerified email at umn.edu
Yaguang LiTexas A&M UniversityVerified email at tamu.edu
Taehyoun OhAssociate Professor of Electrical Engineering, Kwangwoon UniversityVerified email at kw.ac.kr
Rakesh Kumar PalaniAssistant Professor, IIT DelhiVerified email at umn.edu
Sudhir KudvaNvidiaVerified email at nvidia.com
Narasimha LankaIntel corporationVerified email at intel.com
Yishuang LinTexas A&M UniversityVerified email at tamu.edu
Saurabh ChaubeyAnalog Power IC Designer, Texas InstrumentsVerified email at umn.edu

Ramesh Harjani

E. F. Johnson Professor, Electrical & Computer Engineering, University of Minnesota

Verified email at umn.edu - Homepage

Analog Circuits for Communications


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OASYS: A framework for analog circuit synthesis R Harjani, RA Rutenbar, LR Carley IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989	569	1989
A high-efficiency DC–DC converter using 2 nH integrated inductors J Wibben, R Harjani IEEE Journal of Solid-State Circuits 43 (4), 844-854, 2008	384	2008
A low-power CMOS VGA for 50 Mb/s disk drive read channels R Harjani IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1995	277	1995
Design of low-phase-noise CMOS ring oscillators L Dai, R Harjani IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002	156	2002
Fully-integrated on-chip DC-DC converter with a 450X output range SS Kudva, R Harjani IEEE Journal of Solid-State Circuits 46 (8), 1940-1951, 2011	146	2011
A prototype framework for knowledge-based analog circuit synthesis R Harjani, RA Rutenbar, LR Carley Proceedings of the 24th ACM/IEEE Design Automation Conference, 42-49, 1987	144	1987
CMOS switched-op-amp-based sample-and-hold circuit L Dai, R Harjani IEEE journal of solid-state circuits 35 (1), 109-113, 2000	133	2000
Partial positive feedback for gain enhancement of low-power CMOS OTAs R Wang, R Harjani Low-Voltage Low-Power Analog Integrated Circuits: A Special Issue of Analog …, 1995	131	1995
A+ 18 dBm IIP3 LNA in 0.35/spl mu/m CMOS Y Ding, R Harjani 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001	122	2001
A linearized, low phase noise VCO based 25 GHz PLL with automatic biasing B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, J Plouchart, AV Rylyakov, ... IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013	99	2013
Design of high-performance CMOS voltage-controlled oscillators L Dai, R Harjani Springer Science & Business Media, 2003	94	2003
High-frequency LC VCO design using capacitive degeneration B Jung, R Harjani IEEE Journal of Solid-State Circuits 39 (12), 2359-2370, 2004	87	2004
A high-efficiency CMOS +22-dBm linear power amplifier Y Ding, R Harjani Solid-State Circuits, IEEE Journal of 40 (9), 1895-1900, 2005	83	2005
An integrated low-voltage class AB CMOS OTA R Harjani, R Heineke, F Wang IEEE Journal of Solid-State Circuits 34 (2), 134-142, 1999	77	1999
Feasibility and performance region modeling of analog and digital circuits R Harjani, J Shao Analog Integrated Circuits and Signal Processing 10, 23-43, 1996	77	1996
A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter K Nair, R Harjani Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC …, 2004	75	2004
Analog/RF physical layer issues for UWB systems R Harjani, J Harvey, R Sainati 17th International Conference on VLSI Design. Proceedings., 941-948, 2004	71	2004
Correction for pipelined analog to digital (A/D) converter K Nair, R Harjani US Patent 6,784,814, 2004	65	2004
Time-encoded values for highly efficient stochastic circuits MH Najafi, S Jamali-Zavareh, DJ Lilja, MD Riedel, K Bazargan, R Harjani IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (5 …, 2017	64	2017
Fully Integrated Capacitive DC–DC Converter With All-Digital Ripple Mitigation Technique SS Kudva, R Harjani IEEE Journal of Solid-State Circuits 48 (8), 1910-1920, 2013	64	2013

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