| System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation V Bussa, M Dusanapudi, SS Hatti, S Kapoor, RS Moharil, BS Nanjundiah US Patent 7,647,539, 2010 | 47 | 2010 |
| Post-silicon validation of the IBM POWER8 processor A Nahir, M Dusanapudi, S Kapoor, K Reick, W Roesner, KD Schubert, ... Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 30 | 2014 |
| System and method for using resource pools and instruction pools for processor design verification and validation SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, RS Moharil US Patent 7,752,499, 2010 | 28 | 2010 |
| System and method for testing SLB and TLB cells during processor design verification and validation S Bag, M Dusanapudi, SS Hatti, S Kapoor, BNV Satyanarayana US Patent 7,797,650, 2010 | 23 | 2010 |
| System and method for testing a large memory area during processor design verification and validation DS Anvekar, SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor US Patent 7,992,059, 2011 | 22 | 2011 |
| System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation S Arora, SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, ... US Patent 7,661,023, 2010 | 21 | 2010 |
| System and method for re-shuffling test case instruction orders for processor design verification and validation S Arora, S Bag, V Bussa, SR Choudhury, M Dusanapudi, SS Hatti, ... US Patent 7,669,083, 2010 | 19 | 2010 |
| Hardware verification using acceleration platform M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ... US Patent 8,832,502, 2014 | 18 | 2014 |
| System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation S Arora, DS Anvekar, M Dusanapudi, SS Hatti, S Kapoor, BS Nanjundiah US Patent 7,689,886, 2010 | 18 | 2010 |
| System and method for generating fast instruction and data interrupts for processor design verification and validation SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, RS Moharil US Patent 8,099,559, 2012 | 17 | 2012 |
| System and method for pseudo-random test pattern memory allocation for processor design verification and validation SR Choudhury, S Bag, M Dusanapudi, SS Hatti, S Kapoor, ... US Patent 7,584,394, 2009 | 17 | 2009 |
| System and method for efficiently testing cache congruence classes during processor design verification and validation V Bussa, SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, ... US Patent 8,019,566, 2011 | 16 | 2011 |
| System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, C Rayadurgam, ... US Patent 7,747,908, 2010 | 16 | 2010 |
| Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems M Dusanapudi, S Kapoor US Patent 9,612,929, 2017 | 12 | 2017 |
| Test case generation M Dusanapudi, M Kadiyala, J Paul US Patent 9,910,941, 2018 | 11 | 2018 |
| Efficient validation of coherency between processor cores and accelerators in computer systems M Dusanapudi, S Kamaraju, S Kapoor US Patent 9,501,408, 2016 | 11 | 2016 |
| Generating a Test Case Micro Generator During Processor Design Verification and Validation SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, RS Moharil US Patent App. 12/134,255, 2009 | 11 | 2009 |
| Debugging post-silicon fails in the IBM POWER8 bring-up lab M Dusanapudi, S Fields, MS Floyd, GL Guthrie, R Kalla, S Kapoor, ... IBM Journal of Research and Development 59 (1), 12: 1-12: 10, 2015 | 10 | 2015 |
| Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics V Bussa, M Dusanapudi, SS Hatti, S Kapoor US Patent 7,966,521, 2011 | 10 | 2011 |
| System and Method for Efficiently Handling Interrupts SR Choudhury, M Dusanapudi, SS Hatti, S Kapoor, RS Moharil US Patent App. 11/853,208, 2009 | 10 | 2009 |
