| CORDIC architectures: A survey B Lakshmi, AS Dhar VLSI design 2010, 2010 | 116 | 2010 |
| FPGA realization of a CORDIC based FFT processor for biomedical signal processing A Banerjee, AS Dhar, S Banerjee Microprocessors and Microsystems 25 (3), 131-142, 2001 | 91 | 2001 |
| A VLSI array architecture for realization of DFT, DHT, DCT and DST K Maharatna, AS Dhar, S Banerjee Signal Processing 81 (9), 1813-1822, 2001 | 71 | 2001 |
| An array architecture for fast computation of discrete Hartley transform AS Dhar, S Banerjee IEEE transactions on circuits and systems 38 (9), 1095-1098, 1991 | 70 | 1991 |
| CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis KC Ray, AS Dhar IEE Proceedings-Circuits, Devices and Systems 153 (6), 539-544, 2006 | 39 | 2006 |
| Real-time fault-tolerance with hot-standby topology for conditional sum adder A Mukherjee, AS Dhar Microelectronics Reliability 55 (3-4), 704-712, 2015 | 34 | 2015 |
| Architectural design and FPGA implementation of radix-4 CORDIC processor K Bhattacharyya, R Biswas, AS Dhar, S Banerjee Microprocessors and Microsystems 34 (2-4), 96-101, 2010 | 32 | 2010 |
| A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC M Chakraborty, AS Dhar, MH Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (9), 530-534, 2005 | 29 | 2005 |
| VLSI architecture for parallel radix-4 CORDIC B Lakshmi, AS Dhar Microprocessors and Microsystems 37 (1), 79-86, 2013 | 23 | 2013 |
| VLSI architecture for low latency radix-4 CORDIC B Lakshmi, AS Dhar Computers & Electrical Engineering 37 (6), 1032-1042, 2011 | 23 | 2011 |
| FPGA implementation of discrete fractional Fourier transform M Prasad, KC Ray, AS Dhar 2010 International Conference on Signal Processing and Communications (SPCOM …, 2010 | 20 | 2010 |
| CORDIC unit K Maharatna, E Grass, B Swapna, DA Sundar US Patent 7,606,852, 2009 | 20 | 2009 |
| Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs A Palchaudhuri, AS Dhar 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 18 | 2016 |
| A variable RF carrier modulation scheme for ultralow power wireless body-area network A Ghosh, A Halder, AS Dhar IEEE Systems Journal 6 (2), 305-316, 2011 | 15 | 2011 |
| Pipelined VLSI architecture using CORDIC for transform domain equalizer A Banerjee, AS Dhar Journal of Signal Processing Systems 70, 39-48, 2013 | 14 | 2013 |
| High throughput VLSI architecture for one dimensional median filter VVR Teja, KC Ray, I Chakrabarti, AS Dhar 2008 International Conference on Signal Processing, Communications and …, 2008 | 13 | 2008 |
| High performance VLSI architecture for three-step search algorithm R Mukherjee, K Sheth, AS Dhar, I Chakrabarti, S Sengupta Circuits, Systems, and Signal Processing 34, 1595-1612, 2015 | 12 | 2015 |
| High speed architectural implementation of CORDIC algorithm B Lakshmi, AS Dhar TENCON 2008-2008 IEEE Region 10 Conference, 1-5, 2008 | 12 | 2008 |
| Sampled analog architecture for DCT and DST AK Mal, A Basu, AS Dhar 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No …, 2004 | 12 | 2004 |
| Multiplierless array architecture for computing discrete cosine transform MC Mandal, AS Dhar, S Banerjee Computers & electrical engineering 21 (1), 13-19, 1995 | 12 | 1995 |
