Marc Daumas
Marc Daumas
Professeur d'informatique, Université de Perpignan, Laboratoire PROMES
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IEEE standard for floating-point arithmetic
D Zuras, M Cowlishaw, A Aiken, M Applegate, D Bailey, S Bass, ...
IEEE Std 754 (2008), 1-70, 2008
Barra: A parallel functional simulator for gpgpu
S Collange, M Daumas, D Defour, D Parello
2010 IEEE International Symposium on Modeling, Analysis and Simulation of …, 2010
A generic library for floating-point numbers and its application to exact computing
M Daumas, L Rideau, L Théry
International Conference on Theorem Proving in Higher Order Logics, 169-184, 2001
Certification of bounds on expressions involving rounded operators
M Daumas, G Melquiond
ACM Transactions on Mathematical Software (TOMS) 37 (1), 2, 2010
Guaranteed proofs using interval arithmetic
M Daumas, G Melquiond, C Munoz
17th IEEE Symposium on Computer Arithmetic (ARITH'05), 188-195, 2005
Verified real number calculations: A library for interval arithmetic
M Daumas, D Lester, C Munoz
IEEE Transactions on Computers 58 (2), 226-237, 2008
Representable correcting terms for possibly underflowing floating point operations
S Boldo, M Daumas
Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 79-86, 2003
Qualité des calculs sur ordinateur-vers des arithmétiques plus fiables
M Daumas, JM Muller
Paris, Masson, Coll. Informatique, 1997
Modular range reduction: A new algorithm for fast and accurate computation of the elementary functions
M Daumas, C Mazenc, X Merrheim, JM Muller
J. UCS The Journal of Universal Computer Science, 162-175, 1996
Theorems on efficient argument reductions
RC Li, S Boldo, M Daumas
Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 129-136, 2003
A simple test qualifying the accuracy of Horner's rule for polynomials
S Boldo, M Daumas
Numerical Algorithms 37 (1), 45-60, 2004
Recoders for partial compression and rounding.
M Daumas, DW Matula
Division of floating point expansions with an application to the computation of a determinant
M Daumas, C Finot
Journal of Universal Computer Science 5 (6), 323-338, 1999
A Booth multiplier accepting both a redundant or a non redundant input with no additional delay
M Daumas, DW Matula
Proceedings IEEE International Conference on Application-Specific Systems …, 2000
Using graphics processors for parallelizing hash-based data carving
S Collange, YS Dandass, M Daumas, D Defour
2009 42nd Hawaii International Conference on System Sciences, 1-10, 2009
Generating formally certified bounds on values and round-off errors
M Daumas, G Melquiond
Real Numbers and Computers, 55-70, 2004
Validated roundings of dot products by sticky accumulation
M Daumas, DW Matula
IEEE Transactions on Computers 46 (5), 623-629, 1997
Further reducing the redundancy of a notation over a minimally redundant digit set
M Daumas, DW Matula
The Journal of VLSI Signal Processing 33 (1), 7-18, 2003
Formally verified argument reduction with a fused multiply-add
S Boldo, M Daumas, RC Li
IEEE Transactions on Computers 58 (8), 1139-1145, 2008
Multiplications of floating point expansions
M Daumas
Computer Arithmetic, 1999. Proceedings. 14th IEEE Symposium on, 250-257, 1999
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