Magnus Jahre
Magnus Jahre
Verified email at idi.ntnu.no - Homepage
Title
Cited by
Cited by
Year
Finn: A framework for fast, scalable binarized neural network inference
Y Umuroglu, NJ Fraser, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 2017 ACM/SIGDA International Symposium on Field†…, 2017
5562017
Experimental validation of the learning effect for a pedagogical game on computer fundamentals
G Sindre, L Natvig, M Jahre
IEEE Transactions on Education 52 (1), 10-18, 2008
852008
Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform
Y Umuroglu, D Morrison, M Jahre
2015 25th International Conference on Field Programmable Logic and†…, 2015
462015
Scaling binarized neural networks on reconfigurable logic
NJ Fraser, Y Umuroglu, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and†…, 2017
432017
The READEX formalism for automatic tuning for energy efficiency
J Schuchart, M Gerndt, PG Kjeldsberg, M Lysaght, D HorŠk, L ŘŪha, ...
Computing 99 (8), 727-745, 2017
282017
Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks
JM CebriŠn, M Jahre, L Natvig
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014
252014
A light-weight fairness mechanism for chip multiprocessor memory systems
M Jahre, L Natvig
Proceedings of the 6th ACM conference on Computing frontiers, 1-10, 2009
242009
Storage efficient hardware prefetching using delta-correlating prediction tables
M Grannaes, M Jahre, L Natvig
Journal of Instruction-Level Parallelism 13, 1-16, 2011
222011
TULIPP: Towards ubiquitous low-power image processing platforms
T Kalb, L Kalms, D GŲhringer, C Pons, F Marty, A Muddukrishna, M Jahre, ...
2016 International Conference on Embedded Computer Systems: Architectures†…, 2016
212016
ParVec: vectorizing the PARSEC benchmark suite
JM Cebrian, M Jahre, L Natvig
Computing 97 (11), 1077-1100, 2015
202015
An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators
Y Umuroglu, M Jahre
The 32nd IEEE International Conference on Computer Design (ICCD), 2014
192014
EPIC: An energy-efficient, high-performance GPGPU computing research infrastructure
M Sjšlander, M Jahre, G Tufte, N Reissmann
arXiv preprint arXiv:1912.05848, 2019
182019
Supporting utilities for heterogeneous embedded image processing platforms (STHEM): An overview
A Sadek, A Muddukrishna, L Kalms, A Djupdal, A Podlubne, A Paolillo, ...
International Symposium on Applied Reconfigurable Computing, 737-749, 2018
152018
A vector caching scheme for streaming fpga spmv accelerators
Y Umuroglu, M Jahre
International Symposium on Applied Reconfigurable Computing, 15-26, 2015
142015
Get Out of the Valley: Power-Efficient Address Mapping for GPUs
Y Liu, X Zhao, M Jahre, Z Wang, X Wang, Y Luo, L Eeckhout
International Symposium on Computer Architecture (ISCA), 2018
132018
A high performance adaptive miss handling architecture for chip multiprocessors
M Jahre, L Natvig
Transactions on High-Performance Embedded Architectures and Compilers IV, 1-20, 2011
132011
A quantitative study of memory system interference in chip multiprocessor architectures
M Jahre, M Grannaes, L Natvig
2009 11th IEEE International Conference on High Performance Computing and†…, 2009
122009
Streamlined deployment for quantized neural networks
Y Umuroglu, M Jahre
arXiv preprint arXiv:1709.04060, 2017
112017
A study of energy and locality effects using space-filling curves
N Reissman, JC Meyer, M Jahre
2014 IEEE International Parallel & Distributed Processing Symposium†…, 2014
112014
Performance effects of a cache miss handling architecture in a multi-core processor
M Jahre, L Natvig
112007
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Articles 1–20