| The SPLASH-2 programs: Characterization and methodological considerations SC Woo, M Ohara, E Torrie, JP Singh, A Gupta ACM SIGARCH computer architecture news 23 (2), 24-36, 1995 | 5450 | 1995 |
| The performance advantages of integrating block data transfer in cache-coherent multiprocessors SC Woo, JP Singh, JL Hennessy ACM SIGPLAN Notices 29 (11), 219-229, 1994 | 155 | 1994 |
| Methodological considerations and characterization of the SPLASH-2 parallel application suite SC Woo, M Ohara, E Torrie, JP Singh, A Gupta Proceedings of the 22nd Annual International Symposium on Computer …, 1995 | 136 | 1995 |
| Memory controller with power management logic EK Tsern, R Satagopan, RM Barth, SC Woo US Patent 7,003,639, 2006 | 133 | 2006 |
| Memory module with offset data lines and bit line swizzle configuration BW Garrett Jr, FA Ware, CE Hampel, RM Barth, D Stark, AM Abhyankar, ... US Patent 6,839,266, 2005 | 130 | 2005 |
| Methods and systems for reducing heat flux in memory systems SC Woo, CE Hampel US Patent 6,552,948, 2003 | 117 | 2003 |
| System and method for improving performance in computer memory systems supporting multiple memory access latencies SC Woo, BH Tsang US Patent 7,222,224, 2007 | 113 | 2007 |
| Integrated circuit memory system having dynamic memory bank count and page size S Woo, M Ching, CA Bellows, WS Richardson, KT Knorpp, J Kim US Patent 7,254,075, 2007 | 105 | 2007 |
| Apparatus and method for thermal regulation in memory subsystems SC Woo, R Satagopan, RM Barth, EK Tsern, CE Hampel US Patent 6,373,768, 2002 | 102 | 2002 |
| Prototyping a hybrid main memory using a virtual machine monitor D Ye, A Pavuluri, CA Waldspurger, B Tsang, B Rychlik, S Woo 2008 IEEE International Conference on Computer Design, 272-279, 2008 | 85 | 2008 |
| Consolidation of allocated memory to reduce power consumption SC Woo, P Batra US Patent 6,742,097, 2004 | 85 | 2004 |
| ªThe SPLASH-2 Programs: Characterization and Methodological Considerations SC Woo, M Ohara, E Torrie, JP Singh, A Gupta º Proc. 22nd Ann. Int'l Symp. Computer Architecture, 24-36, 1995 | 75 | 1995 |
| Atomic-operation coalescing technique in multi-chip systems Q Lin, L Peng, CE Hampel, TJ Sheffler, SC Woo, B Rychlik US Patent 8,473,681, 2013 | 70 | 2013 |
| Methods and systems for reducing heat flux in memory systems SC Woo, CE Hampel US Patent 6,349,050, 2002 | 69 | 2002 |
| Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device FA Ware, E Tsern, S Woo, RE Perego US Patent 7,454,555, 2008 | 65 | 2008 |
| Adaptive-allocation of I/O bandwidth using a configurable interconnect topology M Ching, S Woo US Patent 7,158,536, 2007 | 65 | 2007 |
| Gupta. The SPLASH-2 programs: Characterization and methodological considerations S Woo, M Ohara, E Torrie, JP Singh International Symposium on Computer Architecture 1995, 1995 | 62 | 1995 |
| High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes BW Garrett Jr, FA Ware, CE Hampel, RM Barth, D Stark, AM Abhyankar, ... US Patent 6,370,668, 2002 | 61 | 2002 |
| Methods and systems for mapping a peripheral function onto a legacy memory interface RE Perego, P Batra, S Woo, L Lai, CM Yeung US Patent 9,043,513, 2015 | 56 | 2015 |
| Memory system with channel multiplexing of multiple memory devices BW Garrett Jr, FA Ware, CE Hampel, RM Barth, DC Stark, AM Abhyankar, ... US Patent 6,708,248, 2004 | 56 | 2004 |
