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| Advanced memory device having reduced power and improved performance PW Coteus, DM Dreps, KC Gower, HC Hunter, CA Kilmer, K Kim, ... US Patent 7,948,817, 2011 | 80 | 2011 |
| Smarter memory: Improving bandwidth for streamed references SA McKee, RH Klenke, KL Wright, WA Wulf, MH Salinas, JH Aylor, ... Computer 31 (7), 54-63, 1998 | 69 | 1998 |
| Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system RK Arimilli, RA Cargnoni, DE Williams, KL Wright US Patent 7,493,417, 2009 | 61 | 2009 |
| Design and evaluation of dynamic access ordering hardware SA McKee, A Aluwihare, BH Clark, RH Klenke, TC Landon, CW Oliver, ... Proceedings of the 10th international conference on Supercomputing, 125-132, 1996 | 60 | 1996 |
| Access request for a data processing system having no system memory R Arimilli, J Dodson, S Ghai, K Wright US Patent App. 10/318,527, 2004 | 58 | 2004 |
| Distributed database transaction protocol J Lee, CG Park, KH Kim, DK Kim US Patent 10,268,743, 2019 | 55* | 2019 |
| Do superconducting processors really need cryogenic memories? The case for cold DRAM F Ware, L Gopalakrishnan, E Linstadt, SA McKee, T Vogelsang, KL Wright, ... Proceedings of the International Symposium on Memory Systems, 183-188, 2017 | 43 | 2017 |
| Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network RK Arimilli, RA Cargnoni, DE Williams, KL Wright US Patent 7,360,067, 2008 | 43 | 2008 |
| Personal information system KL Wright, C La Guardia, CM Duma US Patent 7,979,387, 2011 | 42 | 2011 |
| Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes JS Dodson, JS Fields Jr, GL Guthrie, KL Wright US Patent 7,284,097, 2007 | 42 | 2007 |
| Shared archives in interconnected content-addressable storage systems J Canessa, K Wright US Patent 8,799,221, 2014 | 36 | 2014 |
| Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response R Rajamony, H Shafi, DE Williams, KL Wright US Patent 7,409,504, 2008 | 31 | 2008 |
| Verification of global coherence in a multi-node NUMA system SR Farago, LH Leu, LA Mcconville, KL Wright US Patent 6,785,773, 2004 | 29 | 2004 |
| Methods, systems, and computer program products for dynamic selective memory mirroring JA O'connor, K Bahri, DJ Henderson, LA Lastras-Montano, WE Maule, ... US Patent 8,099,570, 2012 | 28 | 2012 |
| Memory system with dynamic supply voltage scaling K Kim, PW Coteus, A Gara, V Patel, KL Wright US Patent App. 12/326,126, 2010 | 27 | 2010 |
| Three dimensional (3D) memory device sparing ER Cordero, AB Lingambudi, S Sethuraman, KL Wright US Patent 8,869,007, 2014 | 25 | 2014 |
| Isolation of faulty links in a transmission medium JS Dodson, FD Ferraiolo, MM Franceschini, KC Gower, A Jagmohan, ... US Patent 8,862,944, 2014 | 25 | 2014 |
| Cloud based viewing, transfer and storage of medical data K Wright, JC Canessa, G Canessa US Patent App. 13/656,342, 2014 | 24 | 2014 |
| Method and system of managing virtualized physical memory in a data processing system RK Arimilli, JS Dodson, S Ghai, KL Wright US Patent 6,920,521, 2005 | 23 | 2005 |
Saravanan SethuramanIntel CorporationVerified email at intel.com
