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Chetan D Parikh
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Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs
S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi
IEEE Transactions on Electron Devices 47 (4), 789-796, 2000
642000
A new charge-control model for single-and double-heterojunction bipolar transistors
CD Parikh, FA Lindholm
IEEE transactions on electron devices 39 (6), 1303-1311, 1992
601992
A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique
S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi
IEEE Transactions on Electron Devices 47 (1), 171-177, 2000
432000
A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique
S Mahapatra, CD Parikh, VR Rao, CR Viswanathan, J Vasi
IEEE Transactions on Electron Devices 47 (1), 171-177, 2000
432000
Space-charge region recombination in heterojunction bipolar transistors
CD Parikh, FA Lindholm
IEEE transactions on electron devices 39 (10), 2197-2205, 1992
431992
Modeling of the CoolMOS/sup TM/transistor-Part I: Device physics
BJ Daniel, CD Parikh, MB Patil
IEEE Transactions on Electron Devices 49 (5), 916-922, 2002
392002
A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs
S Mahapatra, CD Parikh, J Vasi, VR Rao, CR Viswanathan
Solid-State Electronics 43 (5), 915-922, 1999
321999
Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/using theory of novel voltage sustaining layer
PN Kondekar, CD Parikh, MB Patil
2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference …, 2002
302002
Modeling of the CoolMOS/sup TM/transistor. II. DC model and parameter extraction
BJ Daniel, CD Parikh, MB Patil
IEEE Transactions on Electron Devices 49 (5), 923-929, 2002
212002
100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric
S Mahapatra, VR Rao, KNM Rani, CD Parikh, J Vasi, B Cheng, M Khare, ...
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 1999
191999
Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/MNSFETs
S Mahapatra, VR Rao, B Cheng, M Khare, CD Parikh, JCS Woo, JM Vasi
IEEE Transactions on Electron Devices 48 (4), 679-684, 2001
172001
A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping
S Mahapatra, VR Rao, CD Parikh, J Vasi, B Cheng, JCS Woo
Microelectronic engineering 48 (1-4), 193-196, 1999
141999
A new" multifrequency" charge pumping technique to profile hot-carrier-induced interface-state density in nMOSFET's
S Mahapatra, CD Parikh, J Vasi
IEEE Transactions on Electron Devices 46 (5), 960-967, 1999
141999
Analysis and design of superjunction power MOSFET: CoolMOS/spl trade/for improved on resistance and breakdown voltage using theory of novel voltage sustaining layer
PN Kondekar, MB Patil, CD Parikh
2002 23rd International Conference on Microelectronics. Proceedings (Cat. No …, 2002
122002
A compact model for the N-well resistor
CD Parikh, RM Patrikar
Solid-State Electronics 43 (3), 683-685, 1999
101999
Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET
VR Bhumireddy, KA Shaik, A Amara, S Sen, CD Parikh, D Nagchoudhuri, ...
2013 IEEE International Conference on Circuits and Systems (ICCAS), 1-4, 2013
92013
Modeling power VDMOSFET transistors: Device physics and equivalent circuit model with parameter extraction
R Vaid, N Padha, A Kumar, RS Gupta, CD Parikh
CSIR, 2004
92004
Modelling of a depletion-mode MOSFET
CD Parikh, J Vasi
Solid-state electronics 30 (7), 699-703, 1987
91987
A new delay model and geometric programming-based design automation for latched comparators
A Purushothaman, CD Parikh
Circuits, Systems, and Signal Processing 34 (9), 2749-2764, 2015
82015
Magnetic field effects in a photoconductive switch
CD Parikh, FA Lindholm
Journal of applied physics 64 (11), 6546-6551, 1988
71988
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