| On-chip communication and synchronization mechanisms with cache-integrated network interfaces SG Kavadias, MGH Katevenis, M Zampetakis, DS Nikolopoulos Proceedings of the 7th ACM international conference on Computing frontiers …, 2010 | 41* | 2010 |
| FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability G Kalokerinos, V Papaefstathiou, G Nikiforos, S Kavadias, M Katevenis, ... 2009 International Symposium on Systems, Architectures, Modeling, and …, 2009 | 36 | 2009 |
| Architecture and application of PLATO, a reconfigurable active network platform A Dollas, D Pnevmatikatos, N Aslanides, S Kavvadias, E Sotiriades, ... The 9th Annual IEEE Symposium on Field-programmable Custom Computing …, 2001 | 35 | 2001 |
| Explicit communication and synchronization in SARC M Katevenis, V Papaefstathiou, S Kavadias, D Pnevmatikatos, F Silla, ... IEEE micro 30 (5), 30-41, 2010 | 15 | 2010 |
| Prototyping efficient interprocessor communication mechanisms V Papaefstathiou, D Pnevmatikatos, M Marazakis, G Kalokairinos, ... 2007 International Conference on Embedded Computer Systems: Architectures …, 2007 | 7 | 2007 |
| Rapid prototyping of a reusable 4x4 active ATM switch core with the PCI Pamette A Dollas, D Pnevmatikatos, N Aslamides, S Kavvadias, E Sotiriades, ... Proceedings 12th International Workshop on Rapid System Prototyping. RSP …, 2001 | 7 | 2001 |
| Prototyping a configurable cache/scratchpad memory with virtualized user-level RDMA capability G Kalokerinos, V Papaefstathiou, G Nikiforos, S Kavadias, X Yang, ... Transactions on High-Performance Embedded Architectures and Compilers V, 100-120, 2010 | 6* | 2010 |
| Fine-grain OpenMP runtime support with explicit communication hardware primitives P Tendulkar, V Papaefstathiou, G Nikiforos, S Kavadias, DS Nikolopoulos, ... 2011 Design, Automation & Test in Europe, 1-4, 2011 | 5 | 2011 |
| Low-latency explicit communication and synchronization in scalable multi-core clusters C Kachris, G Nikiforos, V Papaefstathiou, X Yang, S Kavadias, ... 2010 IEEE International Conference On Cluster Computing Workshops and …, 2010 | 5 | 2010 |
| Network processing in multi-core FPGAs with integrated cache-network interface C Kachris, G Nikiforos, S Kavadias, V Papaefstathiou, M Katevenis 2010 International Conference on Reconfigurable Computing and FPGAs, 328-333, 2010 | 4 | 2010 |
| Efficient bandwidth regulation at memory controller for mixed criticality applications G Tsamis, S Kavvadias, A Papagrigoriou, MD Grammatikakis, ... 2016 11th International Symposium on Reconfigurable Communication-centric …, 2016 | 3 | 2016 |
| Dynamic power reduction in self-adaptive embedded systems through benchmark analysis A Scionti, S Kavvadias, R Giorgi 3rd Mediterranean Conference on Embedded Computing (MECO), 62-65, 2014 | 3 | 2014 |
| Embedded reconfigurable computing: the ERA approach G Keramidas, S Wong, F Anjam, A Brandon, R Seedorf, C Scordino, ... 2013 11th IEEE International Conference on Industrial Informatics (INDIN …, 2013 | 3 | 2013 |
| Embedded reconfigurable architectures S Wong, L Carro, S Kavvadias, G Keramidas, F Papariello, C Scordino, ... Proceedings of the 2012 international conference on Compilers, architectures …, 2012 | 3 | 2012 |
| A run-time Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability G Nikiforos, G Kalokairinos, V Papaefstathiou, S Kavadias, ... 6th HiPEAC Industrial Workshop, 1-4, 2008 | 3 | 2008 |
| NP-SARC: Scalable network processing in the SARC multi-core FPGA platform C Kachris, G Nikiforos, V Papaefstathiou, S Kavadias, M Katevenis Journal of Systems Architecture 59 (1), 39-47, 2013 | 2 | 2013 |
| Cache-integrated network interfaces: Flexible on-chip communication and synchronization for large-scale CMPs S Kavadias, M Katevenis, M Zampetakis, DS Nikolopoulos International Journal of Parallel Programming 40 (6), 583-604, 2012 | 2 | 2012 |
| Hardware Support for Explicit Communication in Scalable CMP’s C Villavieja, M Katevenis, N Navarro, D Pnevmatikatos, A Ramirez, ... Computer Architecture Dept., Polythecnic University of Catalonia (UPC) and …, 2008 | 2 | 2008 |
| Network Interface Design for Explicit Communication in Chip Multiprocessors S Kavadias, M Katevenis, D Pnevmatikatos Designing Network On-Chip Architectures in the Nanoscale Era, 363-390, 2010 | 1 | 2010 |
| An fpga-based prototyping platform for research in high-speed interprocessor communication V Papaefstathiou, G Kalokairinos, A Ioannou, M Papamichael, ... 2nd Industrial Workshop of the European Network of Excellence on High …, 2006 | 1 | 2006 |
Manolis G.H. KatevenisFORTH and University of Crete, GreeceVerified email at ics.forth.gr
