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Stefanos Sidiropoulos
Stefanos Sidiropoulos
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Verified email at alumni.stanford.edu
Title
Cited by
Cited by
Year
Weighted round-robin cell multiplexing in a general-purpose ATM switch chip
M Katevenis, S Sidiropoulos, C Courcoubetis
IEEE Journal on selected Areas in Communications 9 (8), 1265-1279, 1991
8041991
A semidigital dual delay-locked loop
S Sidiropoulos, MA Horowitz
IEEE Journal of Solid-State Circuits 32 (11), 1683-1692, 1997
5991997
Integrating receiver with precharge circuitry
JL Zerbe, BW Garlepp, PS Chau, KS Donnelly, MA Horowitz, ...
US Patent 8,199,859, 2012
5152012
Memory system including a point-to-point linked memory subsystem
RE Perego, S Sidiropoulos, E Tsern
US Patent 6,502,161, 2002
4472002
Bus system optimization
JLV Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 6,643,787, 2003
3142003
High-speed electrical signaling: Overview and limitations
M Horowitz, CKK Yang, S Sidiropoulos
IEEE Micro 18 (1), 12-24, 1998
2951998
Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
S Sidiropoulos, D Liu, J Kim, G Wei, M Horowitz
2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 2000
2202000
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
S Sidiropoulos, M Horowitz
IEEE Journal of Solid-State Circuits 32 (5), 681-690, 1997
2011997
Apparatus and method for controlling a master/slave system via master device synchronization
S Sidiropoulos
US Patent 6,839,393, 2005
1942005
A variable-frequency parallel I/O interface with adaptive power-supply regulation
GY Wei, J Kim, D Liu, S Sidiropoulos, MA Horowitz
IEEE Journal of Solid-State Circuits 35 (11), 1600-1610, 2000
1832000
Timing calibration apparatus and method for a memory device signaling system
CE Hampel, RE Perego, SS Sidiropoulos, EK Tsern, FA Ware
US Patent 6,920,540, 2005
1782005
System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
RE Perego, S Sidiropoulos, E Tsern
US Patent 7,010,642, 2006
1542006
Integrated circuit with timing adjustment mechanism and method
JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 6,950,956, 2005
1462005
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
KYK Chang, J Wei, C Huang, S Li, K Donnelly, M Horowitz, Y Li, ...
IEEE Journal of Solid-State Circuits 38 (5), 747-754, 2003
1462003
Phase adjustment apparatus and method for a memory device signaling system
CE Hampel, RE Perego, SS Sidiropoulos, EK Tsern, FA Ware
US Patent 7,668,276, 2010
1452010
Calibrated data communication system and method
JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ...
US Patent 7,042,914, 2006
1452006
System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
RE Perego, S Sidiropoulos, E Tsern
US Patent 7,000,062, 2006
1372006
Clock alignment circuit having a self regulating voltage supply
S Sidiropoulos
US Patent 6,928,128, 2005
1272005
High-performance inter-chip signalling
S Sidiropoulos
Stanford University, 1998
1261998
A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating range
S Sidiropoulos, M Horowitz
1997 IEEE International Solids-State Circuits Conference. Digest of …, 1997
1171997
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