| Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang Microelectronics reliability 49 (6), 642-649, 2009 | 102 | 2009 |
| Efficient techniques for gate leakage estimation RM Rao, JL Burns, A Devgan, RB Brown Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 95 | 2003 |
| SRAM write-ability improvement with transient negative bit-line voltage S Mukhopadhyay, RM Rao, JJ Kim, CT Chuang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (1), 24-32, 2009 | 84 | 2009 |
| High-performance SRAM in nanoscale CMOS: Design challenges and techniques CT Chuang, S Mukhopadhyay, JJ Kim, K Kim, R Rao 2007 IEEE international workshop on memory technology, design and testing, 4-12, 2007 | 82 | 2007 |
| A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits RM Rao, F Liu, JL Burns, RB Brown ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 59 | 2003 |
| Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang 2009 IEEE International Reliability Physics Symposium, 745-749, 2009 | 49 | 2009 |
| A completely digital on-chip circuit for local-random-variability measurement R Rao, KA Jenkins, JJ Kim 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 44 | 2008 |
| Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect CTK Chuang, JJ Kim, TH Kim, PF Lu, S Mukhopadhyay, RM Rao, S Wang US Patent 7,642,864, 2010 | 35 | 2010 |
| Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors JJ Kim, A Bansal, R Rao, SH Lo, CT Chuang IEEE Electron Device Letters 30 (8), 852-854, 2009 | 34 | 2009 |
| On-chip process variation detection using slew-rate monitoring circuit A Ghosh, RM Rao, J Kim, CT Chuang, RB Brown 21st International Conference on VLSI Design (VLSID 2008), 143-149, 2008 | 34 | 2008 |
| Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies RM Rao, JL Burns, RB Brown ESSCIRC 2004-29th European Solid-State Circuits Conference (IEEE Cat. No …, 2003 | 33 | 2003 |
| A local random variability detector with complete digital on-chip measurement circuitry R Rao, KA Jenkins, JJ Kim IEEE Journal of Solid-State Circuits 44 (9), 2616-2623, 2009 | 31 | 2009 |
| 3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4 C Gonzalez, E Fluhr, D Dreps, D Hogenmiller, R Rao, J Paredes, M Floyd, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 50-51, 2017 | 30 | 2017 |
| Parametric yield analysis and constrained-based supply voltage optimization R Rao, K Agarwal, A Devgan, K Nowka, D Sylvester, R Brown Sixth international symposium on quality electronic design (isqed'05), 284-290, 2005 | 30 | 2005 |
| Techniques for improving write stability of memory with decoupled read and write bit lines RV Joshi, JJ Kim, RM Rao US Patent 7,495,969, 2009 | 28 | 2009 |
| FINFET drive strength de-quantization using multiple orientation fins JJ Kim, RM Rao US Patent App. 11/505,224, 2008 | 28 | 2008 |
| Performing logic functions on more than one memory cell within an array of memory cells JB Kuang, RM Rao US Patent 8,493,774, 2013 | 27 | 2013 |
| Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies S Mukhopadhyay, R Rao, JJ Kim, CT Chuang 2008 IEEE International Symposium on Circuits and Systems, 384-387, 2008 | 27 | 2008 |
| Parametric yield analysis and optimization in leakage dominated technologies K Agarwal, R Rao, D Sylvester, R Brown IEEE transactions on very large scale integration (VLSI) systems 15 (6), 613-623, 2007 | 27 | 2007 |
| Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects JJ Kim, R Rao, S Mukhopadhyay, CT Chuang 2008 IEEE International Conference on Integrated Circuit Design and …, 2008 | 26 | 2008 |
Jae-Joon KimProfessor, Seoul National UniversityVerified email at snu.ac.kr
