Vikas Kaushal
Vikas Kaushal
Samsung Semiconductor
Verified email at samsung.com
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Year
A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications
JJ Pekarik, J Adkisson, P Gray, Q Liu, R Camillo-Castillo, M Khater, V Jain, ...
2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 92-95, 2014
822014
Total dose and transient response of SiGe HBTs from a new 4th-generation, 90 nm SiGe BiCMOS technology
NE Lourenco, RL Schmid, KA Moen, SD Phillips, TD England, ...
2012 IEEE Radiation Effects Data Workshop, 1-5, 2012
322012
A study of geometry effects on the performance of ballistic deflection transistor
V Kaushal, I I˝iguez-de-La-Torre, H Irie, G Guarino, WR Donaldson, ...
IEEE Transactions on Nanotechnology 9 (6), 723-733, 2010
262010
Semiconductor device and method of forming the device by forming monocrystalline semiconductor layers on a dielectric layer over isolation regions
JW Adkisson, P Cheng, V Jain, VK Kaushal, Q Liu, JJ Pekarik
US Patent 9,029,229, 2015
242015
Exploring digital logic design using ballistic deflection transistors through Monte Carlo simulations
I ═˝iguez-de-La-Torre, S Purohit, V Kaushal, M Margala, M Gong, ...
IEEE Transactions on Nanotechnology 10 (6), 1337-1346, 2011
142011
Nonlinear electron properties of an InGaAs/InAlAs-based ballistic deflection transistor: Room temperature DC experiments and numerical simulations
V Kaushal, I I˝iguez-de-la-Torre, M Margala
Solid-State Electronics 56 (1), 120-129, 2011
132011
Heterojunction bipolar transistors with an airgap between the extrinsic base and collector
R Camillo-Castillo, V Jain, VK Kaushal, MH Khater, AK Stamper
US Patent 9,159,817, 2015
112015
Study of mutual and self-thermal resistance in 90nm SiGe HBTs
V Jain, B Zetterlund, P Cheng, RA Camillo-Castillo, JJ Pekarik, ...
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 17-20, 2013
102013
Effects of a high-k dielectric on the performance of III–V ballistic deflection transistors
V Kaushal, I ═˝iguez-de-la-Torre, T Gonzßlez, J Mateos, B Lee, V Misra, ...
IEEE electron device letters 33 (8), 1120-1122, 2012
102012
Profile control over a collector of a bipolar junction transistor
R Camillo-Castillo, DL Harame, V Jain, VK Kaushal, MH Khater
US Patent 9,245,951, 2016
82016
Bipolar junction transistors with an air gap in the shallow trench isolation
R Camillo-Castillo, V Jain, VK Kaushal, MH Khater, AK Stamper
US Patent 9,231,074, 2016
82016
Current transport modeling and experimental study of THz room temperature ballistic deflection transistors
V Kaushal, M Margala, Q Yu, P Ampadu, G Guarino, R Sobolewski
Journal of Physics: Conference Series 193 (1), 012092, 2009
82009
Heterojunction bipolar transistor with improved performance and breakdown voltage
R Camillo-Castillo, V Jain, VK Kaushal, MH Khater
US Patent 9,368,608, 2016
72016
Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region
RA Camillo-Castillo, V Jain, VK Kaushal, MH Khater
US Patent 8,946,861, 2015
72015
General purpose logic gate using ballistic nanotransistors
D Wolpert, I I˝iguez-de-la-Torre, V Kaushal, M Margala, P Ampadu
2011 11th IEEE International Conference on Nanotechnology, 1171-1176, 2011
72011
Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region
RA Camillo-Castillo, P Cheng, PB Gray, V Jain, VK Kaushal, MH Khater
US Patent 8,810,005, 2014
62014
Schottky Barrier Diodes in 90nm SiGe BiCMOS process operating near 2.0 THz cut-off frequency
V Jain, P Cheng, BJ Gross, R Camillo-Castillo, JJ Pekarik, JW Adkisson, ...
2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 73-76, 2013
62013
Ballistic deflection transistor: Geometry dependence and boolean operations
I I˝iguez-de-la-Torre, J Mateos, T Gonzßlez, V Kaushal, M Margala
2013 Spanish Conference on Electron Devices, 187-190, 2013
52013
Co-integration of high-performance and high-breakdown SiGe HBTs in a BiCMOS technology
JJ Pekarik, JW Adkisson, R Camillo-Castillo, P Cheng, AW DiVergilio, ...
2012 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1-4, 2012
52012
Heterojunction bipolar transistors with reduced parasitic capacitance
R Camillo-Castillo, V Jain, VK Kaushal, MH Khater
US Patent 9,070,734, 2015
42015
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