Alexandre Eichenberger
Alexandre Eichenberger
Researcher at IBM T.J. Watson Research Center
Verified email at - Homepage
Cited by
Cited by
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,081,501, 2015
Vectorization for SIMD architectures with alignment constraints
AE Eichenberger, P Wu, K O'brien
Acm sigplan notices 39 (6), 82-93, 2004
Optimizing compiler for the cell processor
AE Eichenbergert, K O'Brien, K O'Brien, P Wu, T Chen, PH Oden, ...
14th International Conference on Parallel Architectures and Compilation …, 2005
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
AE Eichenberger, JK O'Brien, KM O'Brien, P Wu, T Chen, PH Oden, ...
IBM Systems Journal 45 (1), 59-84, 2006
Overview of the IBM Blue Gene/P project
G Almasi, S Asaad, RE Bellofatto, HR Bickford, MA Blumrich, B Brezzo, ...
IBM Journal of Research and Development, 2008
OMPT: An OpenMP tools application programming interface for performance analysis
AE Eichenberger, J Mellor-Crummey, M Schulz, M Wong, N Copty, ...
OpenMP in the Era of Low Power Devices and Accelerators: 9th International …, 2013
Efficient SIMD code generation for runtime alignment and length conversion
P Wu, AE Eichenberger, A Wang
International Symposium on Code Generation and Optimization, 153-164, 2005
Effective cluster assignment for modulo scheduling
E Nystrom, AE Eichenberger
Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998
Framework for generating mixed-mode operations in loop-level simdization
AE Eichenberger, KTA Wang, P Wu
US Patent 8,549,501, 2013
Stage scheduling: a technique to reduce the register requirements of a module schedule
AE Eichenberger, ES Davidson
Proceedings of the 28th Annual International Symposium on Microarchitecture …, 1995
Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture
AE Eichenberger, MK Gschwind, JA Gunnels
US Patent 8,650,240, 2014
Automatic creation of tile size selection models
T Yuki, L Renganarayanan, S Rajopadhye, C Anderson, AE Eichenberger, ...
Proceedings of the 8th annual IEEE/ACM international symposium on Code …, 2010
Efficient formulation for optimal modulo schedulers
AE Eichenberger, ES Davidson
ACM SIGPLAN Notices 32 (5), 194-205, 1997
Offloading support for OpenMP in Clang and LLVM
SF Antao, A Bataev, AC Jacob, GT Bercea, AE Eichenberger, G Rokos, ...
2016 Third Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC), 1-11, 2016
An integrated simdization framework using virtual vectors
P Wu, AE Eichenberger, A Wang, P Zhao
Proceedings of the 19th annual international conference on Supercomputing …, 2005
Coordinating GPU threads for OpenMP 4.0 in LLVM
C Bertolli, SF Antao, AE Eichenberger, KOBZ Sura, AC Jacob, T Chen, ...
2014 LLVM Compiler Infrastructure in HPC, 12-21, 2014
Optimum modulo schedules for minimum register requirements
AE Eichenberger, ES Davidson, SG Abraham
ACM International Conference on Supercomputing 25th Anniversary Volume, 227-236, 1995
Hybrid access-specific software cache techniques for the cell be architecture
M Gonzalez, N Vujic, X Martorell, E Ayguadé, AE Eichenberger, T Chen, ...
Proceedings of the 17th international conference on Parallel architectures …, 2008
Multi-petascale highly efficient parallel supercomputer
S Asaad, RE Bellofatto, MA Blocksome, MA Blumrich, P Boyle, ...
US Patent 9,971,713, 2018
Minimum register requirements for a modulo schedule
AE Eichenberger, ES Davidson, SG Abraham
Proceedings of the 27th Annual International Symposium on Microarchitecture …, 1994
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