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Spencer Millican
Spencer Millican
Verifisert e-postadresse på auburn.edu - Startside
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Linear programming formulations for thermal-aware test scheduling of 3D-stacked integrated circuits
SK Millican, KK Saluja
2012 IEEE 21st Asian Test Symposium, 37-42, 2012
242012
Test point insertion using artificial neural networks
Y Sun, S Millican
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 253-258, 2019
182019
Improved random pattern delay fault coverage using inversion test points
S Roy, B Stiene, SK Millican, VD Agrawal
2019 IEEE 28th North Atlantic Test Workshop (NATW), 206-211, 2019
182019
Special session–machine learning in test: A survey of analog, digital, memory, and rf integrated circuits
S Roy, SK Millican, VD Agrawal
2021 IEEE 39th VLSI Test Symposium (VTS), 1-14, 2021
162021
Applying neural networks to delay fault testing: Test point insertion and random circuit training
S Millican, Y Sun, S Roy, V Agrawal
2019 IEEE 28th Asian Test Symposium (ATS), 13-135, 2019
162019
A test partitioning technique for scheduling tests for thermally constrained 3D integrated circuits
SK Millican, KK Saluja
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
132014
Formulating optimal test scheduling problem with dynamic voltage and frequency scaling
SK Millican, KK Saluja
2013 22nd Asian Test Symposium, 165-170, 2013
132013
Special session: delay fault testing-present and future
J Mahmod, S Millican, U Guin, V Agrawal
2019 IEEE 37th VLSI Test Symposium (VTS), 1-10, 2019
122019
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator
S Roy, SK Millican, VD Agrawal
2021 34th International Conference on VLSI Design and 2021 20th …, 2021
102021
Machine Intelligence for Efficient Test Pattern Generation
S Roy, SK Millican, VD Agrawal
2020 IEEE International Test Conference (ITC), 1-5, 2020
82020
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures
S Roy, B Stiene, SK Millican, VD Agrawal
Journal of Electronic Testing 36 (1), 123-133, 2020
82020
Optimal test scheduling of stacked circuits under various hardware and power constraints
SK Millican, KK Saluja
2015 28th International Conference on VLSI Design, 487-492, 2015
72015
Special session: Survey of test point insertion for logic built-in self-test
Y Sun, SK Millican, VD Agrawal
2020 IEEE 38th VLSI Test Symposium (VTS), 1-6, 2020
62020
Unsupervised Learning in Test Generation for Digital Integrated Circuits
S Roy, SK Millican, VD Agrawal
2021 IEEE European Test Symposium (ETS), 1-4, 2021
52021
Principal Component Analysis in Machine Intelligence-Based Test Generation
S Roy, SK Millican, VD Agrawal
2021 IEEE Microelectronics Design & Test Symposium (MDTS), 1-6, 2021
42021
Optimal test scheduling formulation under power constraints with dynamic voltage and frequency scaling
SK Millican, KK Saluja
Journal of Electronic Testing 30 (5), 569-580, 2014
42014
Calculating signal controllability using neural networks: Improvements to testability analysis and test point insertion
J Immanuel, SK Millican
2020 IEEE 29th North Atlantic Test Workshop (NATW), 1-6, 2020
32020
CryptIP: An approach for encrypting intellectual property cores with simulation capabilities
S Millican, P Ramanathan, K Saluja
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
32014
Techniques for faster loading of data for accelerators
MS Fredrickson, J Borkenhagen, MA Muston, SK Millican, JD Irish
US Patent 10,528,399, 2020
12020
Techniques for Debug of Low Power SoCs
S Menon, C Prudvi, R Kuehnis, SS Takhar, S Millican, E Rentschler, ...
2019 20th International Workshop on Microprocessor/SoC Test, Security and …, 2019
12019
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Artikler 1–20