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Thomas B.  Preußer
Thomas B. Preußer
Xilinx Research
Verifisert e-postadresse på utexas.edu - Startside
Tittel
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År
FINN-R An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
M Blott, TB Preußer, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018
4042018
The embedded Java benchmark suite JemBench
M Schoeberl, TB Preusser, S Uhrig
Proceedings of the 8th International Workshop on Java Technologies for Real …, 2010
612010
Inference of quantized neural networks on heterogeneous all-programmable devices
TB Preußer, G Gambardella, N Fraser, M Blott
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 833-838, 2018
532018
Next-generation massively parallel short-read mapping on FPGAs
O Knodel, TB Preußer, RG Spallek
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
502011
Secure, real-time and multi-threaded general-purpose embedded Java microarchitecture
M Zabel, TB Preußer, P Reichel, RG Spallek
10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007
472007
MicroRec: efficient recommendation inference by hardware and data structure solutions
W Jiang, Z He, S Zhang, TB Preußer, K Zeng, L Feng, J Zhang, T Liu, Y Li, ...
Proceedings of Machine Learning and Systems 3, 845-859, 2021
312021
Short-read mapping by a systolic custom FPGA computation
TB Preußer, O Knodel, RG Spallek
2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012
292012
FPGA-specific arithmetic optimizations of short-latency adders
HD Nguyen, B Pasca, TB Preußer
2011 21st International Conference on Field Programmable Logic and …, 2011
292011
Accelerating computations on FPGA carry chains by operand compaction
TB Preußer, M Zabel, RG Spallek
2011 IEEE 20th Symposium on Computer Arithmetic, 95-102, 2011
272011
Optimizing bit-serial matrix multiplication for reconfigurable computing
Y Umuroglu, D Conficconi, L Rasnayake, TB Preusser, M Själander
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (3), 1-24, 2019
252019
Enhancing FPGA device capabilities by the automatic logic mapping to additive carry chains
TB Preußer, RG Spallek
2010 International Conference on Field Programmable Logic and Applications …, 2010
252010
Bump-pointer method caching for embedded Java processors
TB Preußer, M Zabel, RG Spallek
Proceedings of the 5th international workshop on Java technologies for real …, 2007
252007
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
TB Preußer
2017 27th International Conference on Field Programmable Logic and …, 2017
232017
Hyperloglog sketch acceleration on fpga
A Kulkarni, M Chiosa, TB Preußer, K Kara, D Sidler, G Alonso
2020 30th International Conference on Field-Programmable Logic and …, 2020
222020
Mapping basic prefix computations to fast carry-chain structures
TB Preußer, RG Spallek
2009 International Conference on Field Programmable Logic and Applications …, 2009
212009
The SHAP microarchitecture and Java virtual machine
TB Preußer, M Zabel, P Reichel
202007
Skt: A one-pass multi-sketch data analytics accelerator
M Chiosa, TB Preußer, G Alonso
Proceedings of the VLDB Endowment 14 (11), 2369-2382, 2021
182021
Ready PCIe data streaming solutions for FPGAs
TB Preußer, RG Spallek
2014 24th International Conference on Field Programmable Logic and …, 2014
172014
Putting queens in carry chains
TB Preußer, B Nägel, RG Spallek
172009
Putting Queens in Carry Chains, N o̱27
TB Preußer, MR Engelhardt
Journal of Signal Processing Systems 88, 185-201, 2017
162017
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Artikler 1–20