| 3D-stacked memory architectures for multi-core processors GH Loh ACM SIGARCH computer architecture news 36 (3), 453-464, 2008 | 917 | 2008 |
| Die stacking (3D) microarchitecture B Black, M Annavaram, N Brekelbaum, J DeVale, L Jiang, GH Loh, ... 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 781 | 2006 |
| Design space exploration for 3D architectures Y Xie, GH Loh, B Black, K Bernstein ACM Journal on Emerging Technologies in Computing Systems (JETC) 2 (2), 65-103, 2006 | 586 | 2006 |
| Use ECP, not ECC, for hard failures in resistive memories S Schechter, GH Loh, K Strauss, D Burger ACM SIGARCH Computer Architecture News 38 (3), 141-152, 2010 | 480 | 2010 |
| PIPP: Promotion/insertion pseudo-partitioning of multi-core shared caches Y Xie, GH Loh ACM SIGARCH Computer Architecture News 37 (3), 174-183, 2009 | 415 | 2009 |
| Processor design in 3D die-stacking technologies GH Loh, Y Xie, B Black Ieee Micro 27 (3), 31-48, 2007 | 413 | 2007 |
| Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design MK Qureshi, GH Loh 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 235-246, 2012 | 333 | 2012 |
| Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems R Ausavarungnirun, KKW Chang, L Subramanian, GH Loh, O Mutlu ACM SIGARCH Computer Architecture News 40 (3), 416-427, 2012 | 310 | 2012 |
| Efficiently enabling conventional block sizes for very large die-stacked DRAM caches GH Loh, MD Hill Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 308 | 2011 |
| Thermal analysis of a 3D die-stacked high-performance microprocessor K Puttaswamy, GH Loh Proceedings of the 16th ACM Great Lakes symposium on VLSI, 19-24, 2006 | 224 | 2006 |
| 3D-MAPS: 3D massively parallel processor with stacked memory SK Lim, SK Lim Design for High Performance, Low Power, and Reliable 3D Integrated Circuits …, 2013 | 218 | 2013 |
| Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories MR Meswani, S Blagodurov, D Roberts, J Slice, M Ignatowski, GH Loh 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 217 | 2015 |
| Unison cache: A scalable and effective die-stacked DRAM cache D Jevdjic, GH Loh, C Kaynak, B Falsafi 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 25-37, 2014 | 208 | 2014 |
| Thermal herding: Microarchitecture techniques for controlling hotspots in high-performance 3D-integrated processors K Puttaswamy, GH Loh 2007 IEEE 13th International Symposium on High Performance Computer …, 2007 | 201 | 2007 |
| Increasing TLB reach by exploiting clustering in page translations B Pham, A Bhattacharjee, Y Eckert, GH Loh 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 176 | 2014 |
| Dynamic classification of program memory behaviors in CMPs Y Xie, G Loh the 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2008 | 170 | 2008 |
| Enabling interposer-based disintegration of multi-core processors A Kannan, NE Jerger, GH Loh Proceedings of the 48th international symposium on Microarchitecture, 546-558, 2015 | 168 | 2015 |
| Managing GPU concurrency in heterogeneous architectures O Kayiran, NC Nachiappan, A Jog, R Ausavarungnirun, MT Kandemir, ... 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 114-126, 2014 | 168 | 2014 |
| Zesto: A cycle-level simulator for highly detailed microarchitecture exploration GH Loh, S Subramaniam, Y Xie 2009 IEEE International Symposium on Performance Analysis of Systems and …, 2009 | 163 | 2009 |
| Implementing caches in a 3D technology for high performance processors K Puttaswamy, GH Loh 2005 International Conference on Computer Design, 525-532, 2005 | 145 | 2005 |
Mike O'ConnorNVIDIA ResearchVerified email at nvidia.com
