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Giuseppe Tagliavini
Giuseppe Tagliavini
Tenure Track Researcher at University of Bologna
Verified email at unibo.it - Homepage
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Cited by
Cited by
Year
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
1452015
Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
A Pullini, D Rossi, I Loi, G Tagliavini, L Benini
IEEE Journal of Solid-State Circuits 54 (7), 1970-1981, 2019
1372019
A transprecision floating-point platform for ultra-low power computing
G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini
2018 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2018
1272018
Dory: Automatic end-to-end deployment of real-world dnns on low-cost iot mcus
A Burrello, A Garofalo, N Bruschi, G Tagliavini, D Rossi, F Conti
IEEE Transactions on Computers 70 (8), 1253-1268, 2021
1042021
The transprecision computing paradigm: Concept, design, and applications
ACI Malossi, M Schaffner, A Molnos, L Gammaitoni, G Tagliavini, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2018
902018
Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ...
IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021
682021
XpulpNN: Accelerating quantized neural networks on RISC-V processors through ISA extensions
A Garofalo, G Tagliavini, F Conti, D Rossi, L Benini
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 186-191, 2020
512020
Biowolf: A sub-10-mw 8-channel advanced brain–computer interface platform with a nine-core processor and ble connectivity
V Kartsch, G Tagliavini, M Guermandi, S Benatti, D Rossi, L Benini
IEEE transactions on biomedical circuits and systems 13 (5), 893-906, 2019
462019
A transprecision floating-point architecture for energy-efficient embedded computing
S Mach, D Rossi, G Tagliavini, A Marongiu, L Benini
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
452018
4.4 a 1.3 tops/w@ 32gops fully integrated 10-core soc for iot end-nodes with 1.7 μw cognitive wake-up from mram-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021
432021
Flexfloat: A software library for transprecision computing
G Tagliavini, A Marongiu, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2018
412018
Exploring architectural heterogeneity in intelligent vision systems
N Chandramoorthy, G Tagliavini, K Irick, A Pullini, S Advani, S Al Habsi, ...
2015 IEEE 21st International Symposium on High Performance Computerá…, 2015
362015
A mixed-precision RISC-V processor for extreme-edge DNN inference
G Ottavi, A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 512-517, 2020
342020
Design and evaluation of SmallFloat SIMD extensions to the RISC-V ISA
G Tagliavini, S Mach, D Rossi, A Marongiu, L Benini
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 654-657, 2019
332019
Unleashing fine-grained parallelism on embedded many-core accelerators with lightweight OpenMP tasking
G Tagliavini, D Cesarini, A Marongiu
IEEE Transactions on Parallel and Distributed Systems 29 (9), 2150-2163, 2018
332018
GVSoC: a highly configurable, fast and accurate full-platform simulator for RISC-V based IoT processors
N Bruschi, G Haugou, G Tagliavini, F Conti, L Benini, D Rossi
2021 IEEE 39th International Conference on Computer Design (ICCD), 409-416, 2021
322021
Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes
A Garofalo, G Tagliavini, F Conti, L Benini, D Rossi
IEEE Transactions on Emerging Topics in Computing 9 (3), 1489-1505, 2021
322021
Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters
P Burgio, G Tagliavini, A Marongiu, L Benini
2013 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2013
312013
Simplifying many-core-based heterogeneous SoC programming with offload directives
A Marongiu, A Capotondi, G Tagliavini, L Benini
IEEE Transactions on Industrial Informatics 11 (4), 957-967, 2015
292015
ADRENALINE: an OpenVX environment to optimize embedded vision applications on many-core accelerators
G Tagliavini, G Haugou, A Marongiu, L Benini
2015 IEEE 9th International Symposium on Embedded Multicore/Many-coreá…, 2015
282015
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