Walter Stechele
Walter Stechele
Verifisert e-postadresse på tum.de
Sitert av
Sitert av
A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput
C Claus, B Zhang, W Stechele, L Braun, M Hubner, J Becker
2008 International Conference on Field Programmable Logic and Applications …, 2008
Complexity analysis of the emerging MPEG-4 standard as a basis for VLSI implementation
PM Kuhn, W Stechele
Visual Communications and Image Processing'98 3309, 498-509, 1998
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
C Claus, FH Muller, J Zeppenfeld, W Stechele
2007 IEEE International Parallel and Distributed Processing Symposium, 1-7, 2007
Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system
C Claus, J Zeppenfeld, F Muller, W Stechele
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Towards rapid dynamic partial reconfiguration in video-based driver assistance systems
C Claus, R Ahmed, F Altenried, W Stechele
Reconfigurable Computing: Architectures, Tools and Applications: 6th …, 2010
Autovision–a run-time reconfigurable mpsoc architecture for future driver assistance systems (autovision–eine zur laufzeit rekonfigurierbare mpsoc architektur für zukünftige …
C Claus, W Stechele, A Herkersdorf
it-Information Technology 49 (3), 181-187, 2007
An MPEG-7 tool for compression and streaming of XML data
U Niedermeier, J Heuer, A Hutter, W Stechele, A Kaup
Proceedings. IEEE International Conference on Multimedia and Expo 1, 521-524, 2002
Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments
N Alt, C Claus, W Stechele
Proceedings of the conference on Design, automation and test in Europe, 176-181, 2008
An XDL-based busmacro generator for customizable communication interfaces for dynamically and partially reconfigurable systems
C Claus, B Zhang, M Hübner, C Schmutzler, J Becker, W Stechele
Workshop on Reconfigurable Computing Education at ISVLSI 7, 2007
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base
S Vogel, M Liang, A Guntoro, W Stechele, G Ascheid
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
C Claus, R Huitl, J Rausch, W Stechele
2009 International Conference on Field Programmable Logic and Applications …, 2009
Complexity and PSNR comparison of several fast motion estimation algorithms for MPEG-4
PM Kuhn, G Diebel, S Herrmann, A Keil, H Mooshofer, A Kaup, RM Mayer, ...
Applications of Digital Image Processing XXI 3460, 486-499, 1998
Partial reconfiguration on FPGAs in practice—Tools and applications
D Koch, J Torresen, C Beckhoff, D Ziener, C Dennl, V Breuer, J Teich, ...
ARCS 2012, 1-12, 2012
Towards a framework and a design methodology for autonomic SoC
G Lipsa, A Herkersdorf, W Rosenstiel, O Bringmann, W Stechele
Second International Conference on Autonomic Computing (ICAC'05), 391-392, 2005
Mixed frame-/event-driven fast pedestrian detection
Z Jiang, P Xia, K Huang, W Stechele, G Chen, Z Bing, A Knoll
2019 International Conference on Robotics and Automation (ICRA), 8332-8338, 2019
Organic computing at the system on chip level
A Bouajila, J Zeppenfeld, W Stechele, A Herkersdorf, A Bernauer, ...
2006 IFIP International Conference on Very Large Scale Integration, 338-341, 2006
Learning classifier tables for autonomic systems on chip
J Zeppenfeld, A Bouajila, W Stechele, A Herkersdorf
INFORMATIK 2008. Beherrschbare Systeme-dank Informatik. Band 2, 2008
A review of different object recognition methods for the application in driver assistance systems
A Laika, W Stechele
Eighth International Workshop on Image Analysis for Multimedia Interactive …, 2007
A video segmentation algorithm for hierarchical object representations and its implementation
S Herrmann, H Mooshofer, H Dietrich, W Stechele
IEEE transactions on circuits and systems for video technology 9 (8), 1204-1215, 1999
Binarycop: Binary neural network-based covid-19 face-mask wear and positioning predictor on edge devices
N Fasfous, MR Vemparala, A Frickenstein, L Frickenstein, M Badawy, ...
2021 IEEE International Parallel and Distributed Processing Symposium …, 2021
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