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lorenzo chelini
lorenzo chelini
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Near-memory computing: Past, present, and future
G Singh, L Chelini, S Corda, AJ Awan, S Stuijk, R Jordans, H Corporaal, ...
Microprocessors and Microsystems 71, 102868, 2019
1202019
A review of near-memory computing architectures: Opportunities and challenges
G Singh, L Chelini, S Corda, AJ Awan, S Stuijk, R Jordans, H Corporaal, ...
2018 21st Euromicro Conference on Digital System Design (DSD), 608-617, 2018
1182018
Polygeist: Raising C to polyhedral MLIR
WS Moses, L Chelini, R Zhao, O Zinenko
2021 30th International Conference on Parallel Architectures and Compilation …, 2021
662021
Progressive raising in multi-level ir
L Chelini, A Drebes, O Zinenko, A Cohen, N Vasilache, T Grosser, ...
2021 IEEE/ACM International Symposium on Code Generation and Optimization …, 2021
302021
Declarative loop tactics for domain-specific optimization
L Chelini, O Zinenko, T Grosser, H Corporaal
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-25, 2019
272019
TC-CIM: Empowering tensor comprehensions for computing-in-memory
A Drebes, L Chelini, O Zinenko, A Cohen, H Corporaal, T Grosser, ...
10th International Workshop on Polyhedral Compilation Techniques, 2020
222020
OCC: An automated end-to-end machine learning optimizing compiler for computing-in-memory
A Siemieniuk, L Chelini, AA Khan, J Castrillon, A Drebes, H Corporaal, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
202021
Automatic generation of multi-objective polyhedral compiler transformations
L Chelini, T Gysi, T Grosser, M Kong, H Corporaal
Proceedings of the ACM International Conference on Parallel Architectures …, 2020
172020
TDO-CIM: transparent detection and offloading for computation in-memory
K Vadivel, L Chelini, A BanaGozar, G Singh, S Corda, R Jordans, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
152020
Cinm (cinnamon): A compilation infrastructure for heterogeneous compute in-memory and compute near-memory paradigms
AA Khan, H Farzaneh, KFA Friebel, C Fournier, L Chelini, J Castrillon
arXiv preprint arXiv:2301.07486, 2022
132022
Coherently attached programmable near-memory acceleration platform and its application to stencil processing
J Van Lunteren, R Luijten, D Diamantopoulos, F Auernhammer, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 668-673, 2019
122019
Declarative transformations in the polyhedral model
O Zinenko, L Chelini, T Grosser
Inria; ENS Paris-Ecole Normale Supérieure de Paris; ETH Zurich; TU Delft …, 2018
122018
Polygeist: Affine c in mlir
WS Moses, L Chelini, R Zhao, O Zinenko
Not a formal proceedings, 2021
102021
PET-to-MLIR: A polyhedral front-end for MLIR
K Komisarczyk, L Chelini, K Vadivel, R Jordans, H Corporaal
2020 23rd Euromicro Conference on Digital System Design (DSD), 551-556, 2020
102020
LoopOpt: Declarative Transformations Made Easy
L Chelini, M Kong, T Grosser, H Corporaal
Proceedings of the 24th International Workshop on Software and Compilers for …, 2021
12021
SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
Proceedings of the 29th ACM International Conference on Architectural …, 2024
2024
Super-optimization explorer using e-graph rewriting for high-level synthesis
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
US Patent App. 18/396,335, 2024
2024
Program analysis, design space exploration and verification for high-level synthesis via e-graph rewriting
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
US Patent App. 18/396,321, 2024
2024
Towards a high-performance AI compiler with upstream MLIR
R Golin, L Chelini, A Siemieniuk, K Madhu, N Hasabnis, H Pabst, ...
arXiv preprint arXiv:2404.15204, 2024
2024
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR
J Cheng, S Coward, L Chelini, R Barbalho, T Drane
arXiv preprint arXiv:2308.07654, 2023
2023
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Artikler 1–20