| A skew-normal canonical model for statistical static timing analysis S Ramprasath, M Vijaykumar, V Vasudevan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015 | 25 | 2015 |
| GNNIE: GNN inference engine with load-balancing and graph-specific caching S Mondal, SD Manasi, K Kunal, R S, SS Sapatnekar Proceedings of the 59th ACM/IEEE Design Automation Conference, 565-570, 2022 | 13 | 2022 |
| An efficient algorithm for statistical timing yield optimization S Ramprasath, V Vasudevan Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 6 | 2015 |
| Statistical criticality computation using the circuit delay S Ramprasath, V Vasudevan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 6 | 2014 |
| Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. S Ramprasath, V Vasudevan ACM Trans. Design Autom. Electr. Syst. 21 (4), 66:1-66:27, 2016 | 4 | 2016 |
| Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. S Ramprasath, M Madhusudan, AK Sharma, J Poojary, S Yaldiz, ... ISPD, 159-166, 2022 | 3 | 2022 |
| A charge flow formulation for guiding analog/mixed-signal placement T Dhar, S Ramprasath, J Poojary, S Yaldiz, S Burns, R Harjani, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 148-153, 2022 | 3 | 2022 |
| On the computation of criticality in statistical timing analysis S Ramprasath, V Vasudevan Proceedings of the International Conference on Computer-Aided Design, 172-179, 2012 | 3 | 2012 |
| A generalized methodology for well island generation and well-tap insertion in analog/mixed-signal layouts RS Gopalakrishnan, M Madhusudan, AK Sharma, J Poojary, S Yaldiz, ... ACM Transactions on Design Automation of Electronic Systems 28 (5), 1-25, 2023 | 2 | 2023 |
| Machine Learning for Analog Layout SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ... Machine Learning Applications in Electronic Design Automation, 505-544, 2022 | 2 | 2022 |
| Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology M Madhusudan, J Poojary, AK Sharma, S Ramprasath, K Kunal, ... ESSDERC 2023-IEEE 53rd European Solid-State Device Research Conference …, 2023 | 1 | 2023 |
| Exploration of Design/Layout Tradeoffs for RF Circuits using ALIGN J Poojary, S Ramprasath, SS Sapatnekar, R Harjani 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 57-60, 2023 | 1 | 2023 |
| A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, with Efficient Load Balancing and Graph-Specific Caching S Mondal, SD Manasi, K Kunal, S Ramprasath, Z Zeng, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 1 | 2022 |
| A Novel Phoneme Recognition System Using Binary Feature Vector and Correlation Based Classifier J Manikandan, B Venkataramani, S Ramprasath, R Prapanch, G Natesh 2010 International Conference on Advances in Computer Engineering, 198-202, 2010 | 1 | 2010 |
| COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization U Karpuzcu, H Cılasun, W Moy, Z Zeng, T Islam, H Lo, A Vanasse, M Tan, ... | | 2024 |
| Reinforcing the Connection between Analog Design and EDA K Kunal, M Madhusudan, J Poojary, S Ramprasath, AK Sharma, ... 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 665-670, 2024 | | 2024 |
| Automated synthesis of mixed-signal ML inference hardware under accuracy constraints K Kunal, J Poojary, S Ramprasath, R Harjani, SS Sapatnekar 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 478-483, 2024 | | 2024 |
| A Multicore GNN Training Accelerator S Mondal, S Ramprasath, Z Zeng, K Kunal, SS Sapatnekar 2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023 | | 2023 |
| Thursday, March 12, 2015 F Wang, S Yin, M Jun, X Li, T Mukherjee, R Negi, L Pileggi, S Ramprasath, ... | | 2015 |
Sachin SapatnekarUniversity of MinnesotaVerified email at umn.edu
