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Minesh Patel
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LazyPIM: An efficient cache coherence mechanism for processing-in-memory
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ...
IEEE Computer Architecture Letters 16 (1), 46-50, 2016
2212016
Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques
JS Kim, M Patel, AG Yağlıkçı, H Hassan, R Azizi, L Orosa, O Mutlu
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
1952020
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
JS Kim, M Patel, H Hassan, O Mutlu
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
1932018
The reach profiler (reaper) enabling the mitigation of dram retention failures via profiling at aggressive conditions
M Patel, JS Kim, O Mutlu
ACM SIGARCH Computer Architecture News 45 (2), 255-268, 2017
1612017
SIMDRAM: A framework for bit-serial SIMD processing using DRAM
N Hajinazar, GF Oliveira, S Gregorio, JD Ferreira, NM Ghiasi, M Patel, ...
Proceedings of the 26th ACM International Conference on Architectural …, 2021
1512021
CoNDA: Efficient cache coherence support for near-data accelerators
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, R Ausavarungnirun, ...
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
1352019
D-RaNGe: Using commodity DRAM devices to generate true random numbers with low latency and high throughput
JS Kim, M Patel, H Hassan, L Orosa, O Mutlu
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
1242019
Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows
AG Yağlikçi, M Patel, JS Kim, R Azizi, A Olgun, L Orosa, H Hassan, J Park, ...
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
1212021
Are we susceptible to rowhammer? an end-to-end methodology for cloud providers
L Cojocar, J Kim, M Patel, L Tsai, S Saroiu, A Wolman, O Mutlu
2020 IEEE symposium on security and privacy (SP), 712-728, 2020
1172020
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Y Wang, L Orosa, X Peng, Y Guo, S Ghose, M Patel, JS Kim, JG Luna, ...
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
892020
Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability
H Hassan, M Patel, JS Kim, AG Yaglikci, N Vijaykumar, NM Ghiasi, ...
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
892019
A deeper look into rowhammer’s sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
L Orosa, AG Yaglikci, H Luo, A Olgun, J Park, H Hassan, M Patel, JS Kim, ...
MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021
882021
Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines
J Kim, M Patel, H Hassan, O Mutlu
2018 IEEE 36th International Conference on Computer Design (ICCD), 282-291, 2018
852018
QUAC-TRNG: High-throughput true random number generation using quadruple row activation in commodity DRAM chips
A Olgun, M Patel, AG Yağlıkçı, H Luo, JS Kim, FN Bostancı, N Vijaykumar, ...
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
712021
Understanding and modeling on-die error correction in modern DRAM: An experimental study using real devices
M Patel, JS Kim, H Hassan, O Mutlu
2019 49th Annual IEEE/IFIP International Conference on Dependable Systems …, 2019
682019
Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics
M Patel, JS Kim, T Shahroodi, H Hassan, O Mutlu
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020
602020
CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off
H Luo, T Shahroodi, H Hassan, M Patel, AG Yağlıkçı, L Orosa, J Park, ...
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
582020
Reducing DRAM latency via charge-level-aware look-ahead partial restoration
Y Wang, A Tavakkol, L Orosa, S Ghose, NM Ghiasi, M Patel, JS Kim, ...
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
572018
Understanding rowhammer under reduced wordline voltage: An experimental study using real dram devices
AG Yağlıkçı, H Luo, GF De Oliviera, A Olgun, M Patel, J Park, H Hassan, ...
2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems …, 2022
512022
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
AG Yağlikçi, A Olgun, M Patel, H Luo, H Hassan, L Orosa, O Ergin, ...
2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 815-834, 2022
432022
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