| Analyzing dynamic binary instrumentation overhead GR Uh, R Cohn, B Yadavalli, R Peri, R Ayyagari | 72 | 2007 |
| Compiler optimization techniques for exploiting a zero overhead loop mechanism VP Cao, LA Fajardo, S Jinturkar, GR Uh, Y Wang, DB Whalley US Patent 6,367,071, 2002 | 59 | 2002 |
| Timing the WCET of embedded applications W Zhao, P Kulkarni, D Whalley, C Healy, F Mueller, GR Uh Proceedings. RTAS 2004. 10th IEEE Real-Time and Embedded Technology and …, 2004 | 46 | 2004 |
| Effective exploitation of a zero overhead loop buffer GR Uh, Y Wang, D Whalley, S Jinturkar, C Burns, V Cao ACM SIGPLAN Notices 34 (7), 10-19, 1999 | 39 | 1999 |
| Improving performance by branch reordering M Yang, GR Uh, DB Whalley ACM SIGPLAN Notices 33 (5), 130-141, 1998 | 31 | 1998 |
| Efficient and effective branch reordering using profile data M Yang, GR Uh, DB Whalley ACM Transactions on Programming Languages and Systems (TOPLAS) 24 (6), 667-697, 2002 | 28 | 2002 |
| Effectively exploiting indirect jumps GR Uh, DB Whalley Software: Practice and Experience 29 (12), 1061-1101, 1999 | 21 | 1999 |
| Techniques for effectively exploiting a zero overhead loop buffer GR Uh, Y Wang, D Whalley, S Jinturkar, C Burns, V Cao Compiler Construction: 9th International Conference, CC 2000 Held as Part of …, 2000 | 19 | 2000 |
| Experience with a retargetable compiler for a commercial network processor J Kim, S Jung, Y Paek, GR Uh Proceedings of the 2002 international conference on Compilers, architecture …, 2002 | 17 | 2002 |
| An overview of static pipelining I Finlayson, GR Uh, DB Whalley, G Tyson IEEE Computer Architecture Letters 11 (1), 17-20, 2011 | 15 | 2011 |
| Branch elimination by condition merging WC Kreahling, D Whalley, MW Bailey, X Yuan, GR Uh, R van Engelen Software: Practice and Experience 35 (1), 51-74, 2005 | 11 | 2005 |
| Improving low power processor efficiency with static pipelining I Finlayson, GR Uh, D Whalley, G Tyson 2011 15th Workshop on Interaction between Compilers and Computer …, 2011 | 9 | 2011 |
| Branch elimination via multi-variable condition merging W Kreahling, D Whalley, M Bailey, X Yuan, GR Uh, R van Engelen European Conference on Parallel Processing, 261-270, 2003 | 9 | 2003 |
| Coalescing conditional branches into efficient indirect jumps GR Uh, DB Whalley International Static Analysis Symposium, 315-329, 1997 | 8 | 1997 |
| Improving Processor Efficiency by Statically Pipelining Instructions W I. Finlayson, B. Davis, P. Gavin, G. Uh, D ACM SIGPLAN/SIGBED Languages, Compilers, Tools and Theory for Embedded …, 2013 | 7* | 2013 |
| Compiler transformations for effectively exploiting a zero overhead loop buffer GR Uh, Y Wang, D Whalley, S Jinturkar, Y Paek, V Cao, C Burns Software: Practice and Experience 35 (4), 393-412, 2005 | 7 | 2005 |
| Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors D Cho, R Ayyagari, GR Uh, Y Paek International Conference on Compiler Construction, 16-31, 2007 | 3 | 2007 |
| Scheduling instruction effects for a statically pipelined processor B Davis, R Baird, P Gavin, M Själander, I Finlayson, F Rasapour, G Cook, ... 2015 International Conference on Compilers, Architecture and Synthesis for …, 2015 | 2 | 2015 |
| Optimizing transfers of control in the static pipeline architecture R Baird, P Gavin, M Själander, D Whalley, GR Uh Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages …, 2015 | 2 | 2015 |
| Instruction re-selection for iterative modulo scheduling on high performance multi-issue DSPs D Cho, A Ravi, GR Uh, Y Paek International Conference on Embedded and Ubiquitous Computing, 741-754, 2006 | 2 | 2006 |
