| Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC ST Zhou, S Katariya, H Ghasemi, S Draper, NS Kim 2010 IEEE International Conference on Computer Design, 112-117, 2010 | 58 | 2010 |
| Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors HR Ghasemi, SC Draper, NS Kim 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 51 | 2011 |
| Low-cost per-core voltage domain support for power-constrained high-performance processors AA Sinkar, HR Ghasemi, MJ Schulte, UR Karpuzcu, NS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 747-758, 2013 | 42 | 2013 |
| Cost-effective power delivery to support per-core voltage domains for power-constrained processors HR Ghasemi, AA Sinkar, MJ Schulte, NS Kim Proceedings of the 49th Annual Design Automation Conference, 56-61, 2012 | 36 | 2012 |
| RCS: Runtime resource and core scaling for power-constrained multi-core processors HR Ghasemi, NS Kim Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 20 | 2014 |
| Analyzing the impact of joint optimization of cell size, redundancy, and ECC on low-voltage SRAM array total area NS Kim, SC Draper, ST Zhou, S Katariya, HR Ghasemi, T Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011 | 20 | 2011 |
| Array-based inference engine for machine learning A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen US Patent 10,824,433, 2020 | 17 | 2020 |
| An effective VHDL-AMS simulation algorithm with event HR Ghasemi, Z Navabi 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 14 | 2005 |
| Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen US Patent 11,086,633, 2021 | 10 | 2021 |
| Architecture for dense operations in machine learning inference engine A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen US Patent 10,896,045, 2021 | 9 | 2021 |
| Systems and methods for programmable hardware architecture for machine learning A Sodani, CH Chen, UR Hanebutte, HR Ghasemi, S Durakovic US Patent 10,970,080, 2021 | 7 | 2021 |
| Augmenting general purpose processors for network processing HR Ghasemi, H Mohammadi, B Robatmili, N Yazdani Proceedings. 2003 IEEE International Conference on Field-Programmable …, 2003 | 7 | 2003 |
| Workload-adaptive process tuning strategy for power-efficient multi-core processors J Lee, CC Wang, H Ghasemil, L Bircher, Y Cao, NS Kim Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 6 | 2010 |
| VR-scale: Runtime dynamic phase scaling of processor voltage regulators for improving power efficiency H Asghari-Moghaddam, HR Ghasemi, AA Sinkar, I Paul, NS Kim Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
| A new synchronization algorithm for (VHDL-AMS) mixed signal simulation HR Ghasemi, Z Navabi IEEE International Symposium on Communications and Information Technology …, 2004 | 5 | 2004 |
| Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications HR Ghasemi, UR Karpuzcu, NS Kim 2015 33rd IEEE International Conference on Computer Design (ICCD), 304-310, 2015 | 4 | 2015 |
| Architecture of crossbar of inference engine A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen US Patent 11,256,517, 2022 | 3 | 2022 |
| Architecture for irregular operations in machine learning inference engine A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen, R Tan US Patent 11,029,963, 2021 | 3 | 2021 |
| Streaming engine for machine learning architecture A Sodani, U Hanebutte, S Durakovic, HR Ghasemi, CH Chen US Patent App. 16/226,534, 2019 | 3 | 2019 |
| IMPROVING MEMORY RELIABILITY, POWER AND PERFORMANCE USING MIXED-CELL DESIGNS. AR Alameldeen, NS Kim, SM Khan, HR Ghasemi, C Wilkerson, J Kulkarni, ... Intel Technology Journal 17 (1), 2013 | 2 | 2013 |
Nam Sung KimW.J. ‘Jerry’ Sanders III – AMD, Inc. Endowed Chair Professor and Fellow of ACM/IEEEVerified email at illinois.edu
