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Meghna Madhusudan
Meghna Madhusudan
Verified email at umn.edu
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ALIGN: Open-source analog layout automation from the ground up
K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019
812019
A customized graph neural network model for guiding analog IC placement
Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
712020
GANA: Graph convolutional network based automated netlist annotation for analog circuits
K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020
662020
ALIGN: A system for automating analog layout
T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ...
IEEE Design & Test 38 (2), 8-18, 2020
432020
A general approach for identifying hierarchical symmetry constraints for analog circuit layout
K Kunal, J Poojary, T Dhar, M Madhusudan, R Harjani, SS Sapatnekar
Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020
432020
Exploring a machine learning approach to performance driven analog IC placement
Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, S Sapatnekar, R Harjani, ...
2020 IEEE computer society annual symposium on VLSI (ISVLSI), 24-29, 2020
262020
Common-centroid layouts for analog circuits: Advantages and limitations
AK Sharma, M Madhusudan, SM Burns, P Mukherjee, S Yaldiz, R Harjani, ...
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
242021
A circuit attention network-based actor-critic learning approach to robust analog transistor sizing
Y Li, Y Lin, M Madhusudan, A Sharma, S Sapatnekar, R Harjani, J Hu
2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), 1-6, 2021
132021
From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning
J Liu, S Su, M Madhusudan, M Hassanpourghadi, S Saunders, Q Zhang, ...
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
122021
Are analytical techniques worthwhile for analog IC placement?
Y Lin, Y Li, D Fang, M Madhusudan, SS Sapatnekar, R Harjani, J Hu
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 154-159, 2022
92022
Common-centroid layout for active and passive devices: A review and the road ahead
N Karmokar, M Madhusudan, AK Sharma, R Harjani, MPH Lin, ...
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 114-121, 2022
92022
Constructive common-centroid placement and routing for binary-weighted capacitor arrays
N Karmokar, AK Sharma, J Poojary, M Madhusudan, R Harjani, ...
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 166-171, 2022
72022
Fast and efficient constraint evaluation of analog layout using machine learning models
T Dhar, J Poojary, Y Li, K Kunal, M Madhusudan, AK Sharma, SD Manasi, ...
Proceedings of the 26th Asia and South Pacific design automation conference …, 2021
72021
Performance-aware common-centroid placement and routing of transistor arrays in analog circuits
AK Sharma, M Madhusudan, SM Burns, S Yaldiz, P Mukherjee, R Harjani, ...
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
62021
The ALIGN open-source analog layout generator: V1. 0 and beyond
T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020
62020
Amplifier design in weak inversion and strong inversion—A case study
BN Aiyappa, M Madhusudan, B Yashaswini, R Yatish, M Nithin
2017 International Conference on Communication and Signal Processing (ICCSP …, 2017
62017
Analog layout generation using optimized primitives
M Madhusudan, AK Sharma, Y Li, J Hu, SS Sapatnekar, R Hajiani
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
52021
Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs
N Karmokar, AK Sharma, J Poojary, M Madhusudan, R Harjani, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
32023
Design techniques for zero steady-state output ripple in digital low dropout regulators
S Chaubey, M Madhusudan, R Harjani
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems …, 2019
32019
GNN-based hierarchical annotation for analog circuits
K Kunal, T Dhar, M Madhusudan, J Poojary, AK Sharma, W Xu, SM Burns, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
22023
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